Anastacia B. Alvarez

Static Noise Margin of 6T SRAM Cell in 90-nm CMOS

This paper examines the factors that affect the Static Noise Margin (SNM) of a 6T Static Random Access Memory (SRAM) cell designed in 90-nm CMOS. In this paper, the SRAM cell is simulated and noise margins are obtained while varying several parameters that affect SRAM operations. These parameters are temperature, threshold voltage, supply voltage, cell ratio, pull-up ratio, and process corner variations. The simulation results were found to be in agreement with the model derived by Seevinck et al. [1] which is based on the square law device model.

A USB 2.0 controller for an ARM7TDM-S processor implemented in FPGA

In this paper, we present a design of a USB 2.0 interface for ARM7TDM-S system. The whole system is implemented on a Virtex-5 FPGA and uses a separate external USB 2.0 transceiver hardware for signaling requirements. The design is coded in Verilog HDL. The project utilizes the Xilinx ISE Design Suite workflow. The system supports USB communication from the ARM7 system on the FPGA to the USB Host PC, and vice-versa.

Design and implementation of passive RF-DC converters for RF power harvesting systems

In RF energy harvesting scheme, the acquired voltage level is too low to be considered as a supply voltage of applications such as microsensors. Therefore, there is a need to increase this value, and passive voltage multiplier is a solution to this requirement. In this project, two passive voltage multipliers, namely, Modified Dickson (MDVM) and Mandal-Sarpeshkar (MSVM) voltage multipliers are designed and implemented. From a mere input power of 10µW to 60µW at 13.56MHz, the voltage multipliers effectively increased the output voltage to 905mV to 2.128V and 1.114V to 3.609V for MDVM and MSVM, respectively, given a supply voltage of 1V and a capacitive load of 30pF. All designs are implemented using 90nm CMOS process.

Implementation of the Phase II Compiler for the ARM7TDMI-S Dual-Core Microprocessor

The advancement of modern computing machines today is seen in embedded systems by making the system do more functions faster and in real time. One technique is to use multiple processors executing in parallel. Also, because embedded systems have limited memory size, adding more functions in the system will limit the data that can be stored in the memory. This project is an implementation of a compiler for an ARM7TDMI-S microprocessor with dual-core capabilities. Aside from the 32-bit ARM7 instructions, the compiler also includes 16-bit thumb instructions and atomic instructions as its target output. Using thumb instructions compresses the size of the program in the memory to increase the number of data that can be stored in it. Code optimizations and memory optimizations were applied to further take advantage of the use of dual-core microprocessors. Result shows that the compiler gives a good distribution of instructions to the two cores.

A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design

Researches show that the bulk of the power consumption of a processor system goes to the cache memory of the processor. Cache sub-banking and block buffering are the two most common techniques in reducing the power consumption of the cache memory. However, these techniques have only been applied to a single processor. This research study introduces these two techniques to multiprocessor systems. Parallel execution will be the biggest issue that will affect the behavior of the cache sub-banking and block buffering technique. Previous research claimed that the execution of a program spread between more than one processor tends to decrease its locality of reference compared to the same program executing on one processor which will also be studied. This research work created RTL models of cache architectures that implements the cache sub-banking and the block buffering technique. Memory traces were gathered from the M5 simulator which will serve as the stimulus and test bench for the RTL models. The data results showed that inserting a block buffer between level one cache and level two cache in a multiprocessor environment will prove useless because the size of the block buffer will never be enough to sustain the demands of the level one cache. The setup with 1024 set and 8 way which uses 1MB of cache memory is the best architecture to use for a cache architecture with cache sub-banking technique. It produce a miss rate of 12.31% which is an average miss rates from 16 different test bench.

The Effects of Integrated Controller Techniques on the Flash Memories

This paper describes flash controller techniques: (1) split cache memory management which addresses architectural level issues of flash memories; (2) wear levelling and garbage collection which spreads wear-out; (3) density alteration which mitigates the effects of flash cell aging; and (4) Reed-Solomon error correction. All techniques, except RS code, are modelled and simulated in Matlab. The RS code is implemented in 65nm CMOS technology. The proposed controller increased the flash memory lifetime by 128X with a 4.1X increase in latency.

A test port for interfacing and debugging ARM9 processors implemented in FPGA

This paper presents an FPGA implementation of a test port for interfacing and debugging ARM9 processors. The system included a communication interface for debugging the processor, together with the JTAG-based module that granted debugging capability to the selected ARM9 core. Also included was an application software debugger that readily shows the comparison of expected and gathered results from the processor core. The debugging system for the selected ARM9 processor was successfully implemented in a Virtex 5 FPGA development board and was tested using the supported data processing instructions. The latency measured was 0.3 ms per instruction for a baud rate of 4800.

Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL

Improving the performance of on-chip caches has been continually regarded with much effort to provide solution to the increased performance gap between microprocessor and memory. Proposed new design techniques were mostly implemented in software simply because it is easier and faster than hardware implementation. However, with the microprocessor technology advancement, this approach fails to consider other crucial matters such as power and area. To investigate and further evaluate the dynamic partitioning schemes in a shared L2 cache in Chip Multiprocessors (CMP), we have come up with a model to bring together generated traces from the M5 simulator and the hardware implementation of a shared L2 cache described using Verilog Hardware Description Language (HDL) and developed using the Synopsys EDA tools. The use of this system model offers a number of benefits such as the following: (1) L2 cache designs can now be characterized using power and area measurements and not just performance gain alone, (2) processor and L1 caches can be abstracted away from the design to provide more focus, (3) standard benchmark can still be used to evaluate the different designs being compared, and (4) a more realistic design that is closer to getting materialized can be produced.

Comparative study of low-leakage SRAM structures using 90nm CMOS technology

In this paper, we compared two innovations in SRAM structures, the 7T and 8T structures, over the conventional 6T structure. These two structures aim to bring down the total leakage as it becomes one of the limiting factors in submicron design. The three structures were simulated in HSPICE using the 90nm CMOS models under three varying conditions: Typical (1V, 25°C), Best (1.1V, −40°C) and Worst (0.9V, 125°C). Using the simulation results, the three were compared based on the following metrics: leakage current, static noise margin (SNM) and read and write performance. The 8T structure exhibits reduced gate tunneling current by 47.4% and 35.2%, and 83.39% and 97.73% lower in total leakage current than 6T and 7T respectively. The simulation results for SNM also shows that the structure has the greatest improvement by 1.31 times compared to 6T and 7T. For the read ‘0’ operation, 7T and 8T show a degradation performance by 60.8% and 18.1% and also a reduced performance during a write ‘1’ operation by 1.5% and 22% respectively compared to a 6T structure. But for a write ‘0’ operation, 7T and 8T increased their performance by 17.35% and 13.3% respectively compared to 6T.

An Asynchronous Implementation of a 32-bit DLX Microprocessor

Synchronous designs have grown dominant in terms of implementing digital systems because of their simpler design and well established design methodologies. However, using a global clock poses several disadvantages. Asynchronous implementations provide solutions to these problems. In this research, a fully asynchronous 32-bit DLX microprocessor is implemented using the HDL (hardware design language) design flow. The architecture of this system uses an asynchronous pipeline of registers. Sutherland’s control circuit for micropipelines is incorporated to handle the handshaking between the stages of the pipeline. By using the micropipeline concept, additional timing circuitries are added to facilitate the diverse triggering of the asynchronous modules. Post-synthesis characteristics of the final system show a 189.88% increase in the execution time attributed to the return-to-zero property of the four-phase handshaking protocol used in the system. An increase of 15.24% in the area is observed crediting from the unoptimized modules of the asynchronous control circuit. Lastly, a 19.81% decrease in total power consumption is observed on the Asynchronous DLX.