Joy Alinda P. Reyes

Comparative Analysis of Low Power Multiplier Architectures

This paper presents a comparative analysis of four different multiplier architectures. The four multipliers include the array multiplier, a bypass multiplier with tree structure, a multiplier with 2-d bypass, and a bypass multiplier using improved column bypassing schemes. The multipliers a reimplemented in 90nm CMOS technology. The architectures are compared in terms of critical path delay, power dissipation and area in terms of transistor count. The multipliers perform worse compared to the array multiplier in terms of power due to the scaling effects on leakage current. Each of the three multipliers has its own trade-offs between power and delay.

DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache

Data access in main memory units can be sufficient for processors but due to demands for faster computers nowadays, implementation of multiple cores as well as the usage of a cache to increase performance, are necessary. These two solutions were implemented using a 32-bit pipelined DLX microprocessor, resulting to a dual core capable (DCC) DLX with single-level cache in a Uniform Memory Access Architecture type. This project made use of the Shared Cache System divided into an Instruction Cache and a Data Cache to solve processor structural hazards due to coincident instruction and data access.

Dual core capability of a 32-bit DLX microprocessor

We report an implementation of a 32-bit DLX microprocessor capable of operating in a dual core environment. The processor was modified for it to be capable of operating atomic instructions, a requirement in a dual core environment. The dual core environment was simulated using a similar core acting as a pseudo slave core. The resulting processor can then be interfaced with another instance of the same processor to function as a dual core processor. It can also be interfaced with a DSP co-processor that is compatible with the handshaking protocols of the processor. The resulting implementation yielded a power reduction of 17.9% (due to a more efficient register file) and an area overhead of 23% (due to additional blocks needed for dual core capability) compared to previous DLX implementations of the laboratory.

DLX gold: design and implementation of a DLX microprocessor with single precision floating- point operations

Floating point (FP) arithmetic is an integral part of modern processors because numerous programs need to perform FP operations. The project aimed to implement a 32-bit pipelined DLX microprocessor that can handle single precision FP operations. This project made use of the class 1 architecture for FP operations, which has an independent unit for addition, multiplication, and division. Furthermore, dynamic scheduling, specifically the speculative Tomasulo algorithm, was employed to effectively handle the parallel execution of instructions. The structural model was implemented using VHDL (VHSIC hardware description language). Afterwards, the functionality was verified using the Cadencereg design system software. Finally, the schematic and layout were produced also using Cadencereg. The implemented microprocessor was then characterized in terms of speed, area, and power consumption. The addition of the FP Units resulted in a 53% decrease in execution time, with an area and power overheads of 98% and 65% respectively.

High-level implementation of the 5-stage pipelined ARM9TDM core

This paper summarizes a project on the implementation of the ARM9TDM, a 32-bit RISC processor based on the ARM9TDMI. This core is the successor to the ARM7TDMI-S which is used for embedded applications requiring low power, small chip area, and high processing speed. The main features of the ARM9TDM are its use of a 5-stage pipelined datapath and a Harvard architecture that has separate data and instruction interfaces. It supports the ARMv4T instruction set architecture (ISA) that uses both the 32-bit ARM instructions and 16-bit Thumb instructions. It includes a high-speed multiplier and debug capabilities using JTAG boundary scan test interface. It does not include an EmbeddedICE-RT module. The project was coded using the Verilog Hardware Description Language and was simulated using Synopsys VCS. The verified code was synthesized in 0.25-micrometer standard cells using Synopsys Design Vision. The layout generated by Synopsys Astro was characterized as having a maximum operating frequency of 34.13 MHz, an average power consumption of 16mW and a chip size of 1.5335 sq. mm.

High-level implementation of an ARM7 microprocessor with multicore capabilities

This paper presents an implemention of an ARM7 microprocessor with multicore capabilities. The required modifications to support multiprocessing include: the addition of atomic instructions to the instruction set and the addition of a bus interface. The implementation resulted to a 170% power overhead and a decrease in area by 61% compared with the single core implementation of the ARM7 microprocessor in the laboratory. The maximum allowable frequency attained was 17 MHz, an improvement from the previous implementations 10 MHz.

A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design

Researches show that the bulk of the power consumption of a processor system goes to the cache memory of the processor. Cache sub-banking and block buffering are the two most common techniques in reducing the power consumption of the cache memory. However, these techniques have only been applied to a single processor. This research study introduces these two techniques to multiprocessor systems. Parallel execution will be the biggest issue that will affect the behavior of the cache sub-banking and block buffering technique. Previous research claimed that the execution of a program spread between more than one processor tends to decrease its locality of reference compared to the same program executing on one processor which will also be studied. This research work created RTL models of cache architectures that implements the cache sub-banking and the block buffering technique. Memory traces were gathered from the M5 simulator which will serve as the stimulus and test bench for the RTL models. The data results showed that inserting a block buffer between level one cache and level two cache in a multiprocessor environment will prove useless because the size of the block buffer will never be enough to sustain the demands of the level one cache. The setup with 1024 set and 8 way which uses 1MB of cache memory is the best architecture to use for a cache architecture with cache sub-banking technique. It produce a miss rate of 12.31% which is an average miss rates from 16 different test bench.

A study of floating-point architectures for pipelined RISC processors

To achieve an increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs) are used. However, there is a need to analyze the suitability of floating-point architectures for high-speed or low power applications. In this research, different system-level architectures and operational algorithms of FPUs were implemented using 0.25mum CMOS standard cells. Fair comparison of design metrics in terms of speed, area and power consumption were made and analyzed for each design. Simulation results show that architectures with an independent pipeline for division perform better in terms of speed while combined pipelines consume the least power. Also, architectures with a combined pipeline for addition and multiplication and an independent pipeline for division occupy the smallest layout area and, in general, show the best performance in all three metrics

Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL

Improving the performance of on-chip caches has been continually regarded with much effort to provide solution to the increased performance gap between microprocessor and memory. Proposed new design techniques were mostly implemented in software simply because it is easier and faster than hardware implementation. However, with the microprocessor technology advancement, this approach fails to consider other crucial matters such as power and area. To investigate and further evaluate the dynamic partitioning schemes in a shared L2 cache in Chip Multiprocessors (CMP), we have come up with a model to bring together generated traces from the M5 simulator and the hardware implementation of a shared L2 cache described using Verilog Hardware Description Language (HDL) and developed using the Synopsys EDA tools. The use of this system model offers a number of benefits such as the following: (1) L2 cache designs can now be characterized using power and area measurements and not just performance gain alone, (2) processor and L1 caches can be abstracted away from the design to provide more focus, (3) standard benchmark can still be used to evaluate the different designs being compared, and (4) a more realistic design that is closer to getting materialized can be produced.

An Asynchronous Implementation of a 32-bit DLX Microprocessor

Synchronous designs have grown dominant in terms of implementing digital systems because of their simpler design and well established design methodologies. However, using a global clock poses several disadvantages. Asynchronous implementations provide solutions to these problems. In this research, a fully asynchronous 32-bit DLX microprocessor is implemented using the HDL (hardware design language) design flow. The architecture of this system uses an asynchronous pipeline of registers. Sutherland’s control circuit for micropipelines is incorporated to handle the handshaking between the stages of the pipeline. By using the micropipeline concept, additional timing circuitries are added to facilitate the diverse triggering of the asynchronous modules. Post-synthesis characteristics of the final system show a 189.88% increase in the execution time attributed to the return-to-zero property of the four-phase handshaking protocol used in the system. An increase of 15.24% in the area is observed crediting from the unoptimized modules of the asynchronous control circuit. Lastly, a 19.81% decrease in total power consumption is observed on the Asynchronous DLX.