Louis P. Alarcon

Ultralow-Power Design in Near-Threshold Region

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

Exploring Very Low-Energy Logic: A Case Study

This paper shows leakage as a limit to the effectiveness of voltage scaling as a means of reducing the energy per operation in a digital circuit. Methods of decreasing operational or dynamic leakage are then discussed. The design and simulation results of a sense amplifier-based pass transistor logic (SAPTL) circuit topology as a low leakage and low energy alternative is presented and then compared to standard static 90-nm CMOS implementations.

Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic

This paper presents the design and implementation of a low-energy asynchronous logic topology using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low-leakage pass transistor networks at low supply voltages. The introduction of asynchronous operation in SAPTL further improves energy-delay performance without a significant increase in hardware complexity. We show two different self-timed approaches: 1) the bundled data and 2) the dual-rail handshaking protocol. The proposed self-timed SAPTL architectures provide robust and efficient asynchronous computation using a glitch-free protocol to avoid possible dynamic timing hazards. Simulation and measurement results show that the self-timed SAPTL with dual-rail protocol exhibits energy-delay characteristics better than synchronous and bundled data self-timed approaches in 90-nm CMOS.

Active RFID: Perpetual wireless communications platform for sensors

A highly integrated 2.4GHz wireless communications platform for an Active RFID system supporting perpetual operation in indoor lighting conditions is presented. The system requires no external components except an antenna, two BAW resonators, a small solar panel, and a rechargeable battery. It is implemented in 65nm CMOS, comprising of a BAW-based transceiver, digital baseband and integrated power management unit. Including converter losses, the system consumes 850nW when idle, 155μW in receive mode, and 4.7mW in transmit mode.

An aggressive power optimization of the ARM9-based core using RAZOR

With the increasing popularity of mobile and energy-limited devices, the trend in the field of microprocessor design has shifted from high performance to low power operation. A common low power technique is reducing the supply voltage during periods of low utilization. However, this is limited by the safety margins needed to protect the processor from infrequent voltage glitches and environmental noise. On the other hand, as long as all errors can be detected and recovered, a considerable amount of energy can be saved. In this paper, a processor based on the ARM architecture was first implemented and verified, and then the RAZOR technique was integrated to add resiliency. The core with and without RAZOR are then simulated using an FFT program at different supply voltages and clock frequencies. The optimized core achieved a maximum energy reduction of 22% at constant clock frequency, while a 23% performance increase is observed at constant energy consumption.

A Study on the effect of varying voltage supply on the performance of voltage sense amplifiers for 1-Transistor DRAM memories

In this paper, the result of varying the supply voltage on the operation, speed and current supply of four voltage sense amplifier circuits for 1-Transistor DRAM memories is investigated. Utilizing the half-Vdd pre-charge, the sense amplifiers are designed to achieve the highest possible gain and noise margin, and are implemented in a 90 nm CMOS technology. For a supply of 1.2 V, the <i>Current</i> <i>Mirror</i> <i>Sense</i> <i>Amplifier</i> <i>with</i> <i>Cross</i> <i>Latch</i> <i>Stage</i> <i>at</i> <i>the</i> <i>Output</i> achieved the highest gain of -31.4, while the <i>Full</i> <i>Latch</i> <i>Sense</i> <i>Amplifier</i> consumes the least current at 92.2 uA and produces the highest noise margin among the four topologies. Simulations also verify the decrease on the speed of the sense amplifiers with the lowering of the voltage supply as manifested on the slew rate, but with an expected improvement on the current consumption.

Design Methodology for CMOS Low-Noise Amplifiers Using Power Matching Techniques

In this paper, a methodology in designing CMOS low-noise amplifiers (LNAs) is proposed. Three power- matching techniques are considered in the design of the LNA. These are: (1) matching for maximum available gain, (2) matching for a constant gain, and (3) matching for stability. Using a 0.25 mum CMOS process, several LNA circuits employing the common-source topology with cascode configuration are designed, implemented, fabricated, and tested. The performance of LNA circuits designed using the three different techniques are characterized. Simulation and actual measurement results are also compared and analyzed to determine the capability of the simulator to predict the LNAs overall performance at radio frequencies.

Timing analysis and optimization of voltage scaled CMOS digital circuits with dual-V th devices

Supply voltage scaling greatly reduces the power consumption of circuits and is typically used in applications with loose speed constraints but tight power budgets. However, without digital standard cell libraries characterized at low voltages, integration of this technique is difficult in the semi-custom design flow. Thus, digital circuits are synthesized at the nominal voltage and their operating frequency is estimated at low voltages. However, this existing approach does not guarantee the timing of circuits containing standard cells with multiple threshold voltages whose delays scale differently as the supply voltage decreases. Slow high Vth non-critical paths are at risk of becoming critical paths at lower voltages that can cause timing errors. A new framework for timing analysis and removal of violating paths is then proposed for dual-Vth circuits. The framework is integrated in a 65nm CMOS digital flow and is verified using an 8-bit microcontroller core as the input design. The method successfully eliminated violating paths but the 35%-61% delay margin of the standard cell libraries contributed to the delay estimation errors.

Experimental analysis of read related transistors’ gate width sizing effects on the 3T1D DRAM access time curve

Unlike SRAMs, the access time of 3T1D DRAMs increase as the feature size becomes smaller. To combat this slow down, it has been suggested that the sizes of read related transistors be increased, a technique that has never been thoroughly explored. This paper deals with the exploration of the effects of the said technique, focusing on its effectiveness as a function of the width increase and how it holds up as feature sizes get smaller. Our results show that applying such technique sometimes has unexpected and surprising effects, including deviating the access time curve from its expected shape, and worse, even slowing the memory cell down even further at certain times-of-read. We also discovered that the effectiveness of the technique actually becomes more and more limited as feature sizes get smaller. At a smaller feature size, it would no longer be sufficient by itself, and would have to be combined with another technique to speed up the memory cell.

A study of floating-point architectures for pipelined RISC processors

To achieve an increase in the computing performance of embedded microprocessors, improved implementations of floating-point units (FPUs) are used. However, there is a need to analyze the suitability of floating-point architectures for high-speed or low power applications. In this research, different system-level architectures and operational algorithms of FPUs were implemented using 0.25mum CMOS standard cells. Fair comparison of design metrics in terms of speed, area and power consumption were made and analyzed for each design. Simulation results show that architectures with an independent pipeline for division perform better in terms of speed while combined pipelines consume the least power. Also, architectures with a combined pipeline for addition and multiplication and an independent pipeline for division occupy the smallest layout area and, in general, show the best performance in all three metrics