Henricus G. R. Maas

An ultra low-power RF bipolar technology on glass

We present a new technology, SOA (Silicon-On-Anything) to transfer circuits processed on SOI substrates to another substrate, e.g. glass or alumina. We have used this technology to integrate an ultra low-power bipolar high-frequency process with high-quality passive components including spiral inductors. Circuits with record low-power RF performance are demonstrated.

An ultra low power lateral bipolar polysilicon emitter technology on SOI

Until now the lateral bipolar transistor on SOI has been presented as an option in a CMOS process. In this investigation we show that this device structure is also very attractive for purely bipolar applications, enabling high frequency operation at ultra low power levels. Excellent devices with emitter areas down to 0.15 /spl mu/m/sup 2/, with scaled junction capacitances and f/sub T/ as high as 15 GHz are demonstrated. Due to the properly scaled junction capacitances a f/sub max/ of 15 GHz is realised at collector currents as low as 15 /spl mu/A.<<ETX>>

A low-cost substrate transfer technology for fully integrated transceivers

A low-cost post-processing technology to transfer on waferscale, circuits fabricated in any IC process, to an alternative substrate, e.g. glass, is presented. This technology combines the advantages of standard silicon IC processing with a complete freedom of substrate choice and enables the integration of high quality passive components and completely eliminates cross-talk between critical circuit parts.

BASIC: an advanced high-performance bipolar process

A novel high-performance bipolar process suitable for analog applications is described. A self-aligned technology called BASIC (best alignment with sidewall contact) yields a sidewall contacted structure with strongly reduced parasitic capacitances and low base resistance. The base link-up problem, which is of particular importance for analog applications, is eliminated in the BASIC process by the introduction of a well-defined submicron region, into which a link-up base adjustment dose can be implanted. A simple, novel polysilicon planarization method has been used to form sidewall contacted base boosts. The method is based on the controlled diffusion of boron in polysilicon, followed by the selective wet etching of undoped polysilicon. DC and AC characteristics for the npn transistor exhibit a combination of properties that makes this process very suitable for analog applications, featuring a maximum f/sub T/ of 17 GHz and an Early voltage of 80 V. Two-dimensional device simulations indicate that the increase in Early voltage by more than a factor of two for narrow emitters is caused by lateral depletion of the collector region underneath the intrinsic emitter-base region.<<ETX>>

Charge sharing effects in bipolar transistors with sub-halfmicron emitter widths

It is shown by numerical simulation and experiment that, in transistors with a base link-up deeper than the intrinsic base, the electric field in the collector-base junction is reduced for very narrow emitters. This is due to charge sharing of the base link-up and intrinsic collector-base depletion regions in the epi-layer underneath the emitter. These 2-D effect cause a decrease in f/sub T/ and h/sub FE/, but an increase in V/sub eaf/. By keeping the base link-up shallow it is possible to minimize f/sub T/ decrease for narrow emitters. This is demonstrated in a transistor with f/sub T/=24 GHz (V/sub cb/=3 V) and an emitter width W/sub e/=0.1 mu m.<<ETX>>

Optimization of the high-frequency performance of the BASIC bipolar technology

The high-frequency performance of the BASIC bipolar technology has been improved by increasing the cutoff frequency and by a strong reduction of the base resistance. Furthermore, excellent analog performance, inherent to the BASIC device structure, has been maintained.