Andras Vass-Varnai

Measurement based compact thermal model creation - accurate approach to neglect inaccurate TIM conductivity data

In this paper two possible ways are investigated to create accurate thermal models without having validated information on the thermal properties of the applied thermal interface materials. One way is the calibration of a detailed numerical thermal model based on the physical information which can be derived from experimental structure functions. In the paper we show a complete calibration procedure using a TO-220 package as an example. Another approach is the generation of dynamic compact models based on real measurements. In order to apply this approach one has to identify the junction-to-case thermal resistance of the tested package using the JEDEC JESD 51-14 standard.

Package Characterization: Simulations or Measurements?

As the functionality of thermal simulators gets more and more complex, measurement techniques also improve. Thermal engineers face and increasingly difficult task to make the right selection from the existing tools. In this paper the applicability of the JEDEC JESD 51-1 static measurement method is compared to mainstream simulation tools especially MCAD or EDA embedded CFD solutions. Both techniques are opposed to each other in terms of required time and other expense factors. In this paper we discuss when different aspects of trade-offs to be made between thermal simulation and physical testing.

Issues in junction-to-case thermal characterization of power packages with large surface area

There are several ways to define the junction-to-case thermal resistance; however, it is rather challenging to characterize the heat-flow in a package by a single number in an accurate and reproducible way. For many power package families such as TO-type packages the thermal transient testing and the so-called dual interface method can give reliable results. The diverging point of structure functions from dual thermal transients gives a good picture of the material interfaces in such structures. However, the location and nature of the diverging point strongly depends on the shape and direction of the heat-spreading. If the package area is much larger than the dissipating chip the shape of the heat-flow changes when using different interfaces. This causes structure functions corresponding to the two setups deviate much before reaching the case surface. In this paper the origin of this phenomenon is investigated. Measurement and simulation results are compared on different large IGBT modules with several modifications in their structure enabling a detailed analysis of the heat-flow path. A comparison is given between heating only a small fraction of a large module and heating all chips. Some samples went through thermal cycling reliability tests which resulted in cracks below the chips. The effect of the reduced die-attach area is visualized with the help of structure functions.

A detailed IC package numerical model calibration methodology

Experimentally derived structure functions can be used to provide insights into the thermal resistances and capacitances heat experiences as it travels from a die through and beyond an IC package. A 3D “detailed” numerical model of the package that purports to explicitly represent the internal construction of the package requires material properties and geometric sizes to be accurately specified. A structure function derived from simulating the detailed numerical model can itself be compared to the experimentally derived reference example. Deviations between experimental and numerical SFs indicate error sites within the detailed model and an indication of whether the thermal resistances or thermal capacitances of the numerical would need to be increased or decreased to match the experimentally observed values. Iterative modifications of the detailed model, based on successive structure function comparisons, will achieve a fully calibrated detailed numerical package model.

Characterization method for thermal interface materials imitating an in-situ environment

In this paper the aspects of thermal interface material characterization are discussed from a practical point of view. A novel method based on existing measurement standards is introduced for a quick and repeatable thermal conductivity measurement of nanoparticle-based thermal greases. The effect of the surface roughness of the DUT fixture is evaluated, and a method is introduced for the long-term reliability testing of these nanocomposites.

Comparison of JEDEC dynamic and static test methods for the thermal characterization of power LEDs

In this paper we review the history of the static (continuous) and dynamic (pulsed) test methods described in JEDEC JESD51-1 [1]. Written in 1995, there has not been, to date and to the knowledge of the authors, any systematic review to these different approaches to the transient thermal testing of packaged ICs and LEDs. Commercially available and in-house test equipment perform either transient thermal testing according to one approach or the other, but not both.

Simulation based method to eliminate the effect of electrical transients from thermal transient measurements

Thermal transient testing is the industry de-facto test method for the identification of junction temperatures and structural defects inside semiconductor devices. Unfortunately, at the beginning of the thermal transient curve in each case an electric effect can be observed, which appears immediately as the unit power step takes place. This electric effect covers the initial phase of thermal transient, and without knowing it the exact temperature of the device cannot be determined. The current industrial methods make a simple correction by cutting the first stage of the thermal measurement, but it is inaccurate, and the correction requires a manual step, therefore it is uncertain. This article describes a methodology to accurately reproduce the thermal transient curve eliminating the effect of the initial electric transients. We approached the problem by using the combination of thermal transient simulation and measurements, fitting the simulated results to the measured curve knowing that the second half of the measured curve certainly reflects the reality.

Failure prediction of IGBT modules based on power cycling tests

This article describes a possible method to assess the long-time behaviour of IGBT modules using the combination of power cycles to stress the devices and thermal transient testing to monitor possible die-attach degradation. The failure of an IGBT module is a complex phenomenon; it consists of thermal, electrical and thermo-mechanical effects. After a theoretical overview of the possible mechanisms, a detailed description on the structure of selected IGBT module and the power cycling parameters is given. To better understand the temperature distribution on the device and the reason of the failure after the cycling, the module was opened up, inspected visually and an equivalent thermal model was built and calibrated to the physical test results. Failure mechanisms such as die attach resistance increase, wire bond cracking and gate oxide degradation were detected.

Thermal transient analysis of semiconductor device degradation in power cycling reliability tests with variable control strategies

In this article we investigate the different failure mechanisms in IGBT modules as a result of power cycling tests. The power cycling is carried out with different control strategies, such as constant current load, constant power and constant junction temperature. With the continuous monitoring of the tested device voltage, junction temperatures and periodic thermal transient tests, the crack of the wire bonds or even degradation of the die attach layer can be identified. A comparison between the effects of the studied control strategies on the lifetime of the tested device is also presented.

Transient thermal characterization of a fcBGA-H device

In this paper, we describe a study in which the thermal performance data of Theta jc (Rth-JC), Theta ja (Rth-JA), and structure functions of a flip-chip ball grid array device with heat spreader, fcBGA-H, was measured. For Rth-JC, various boundary conditions for the thermal resistance modeling were considered and are discussed here. A transient measurement method was used to obtain the temperature responses of the diodes. The structure functions of the diodes were measured; and the thermal resistances were calculated. Furthermore, the effect of power map on the structure functions was studied, and a thermal simulation was conducted to match the simulated structure functions with the experimental structure functions. The matched simulation structure functions provides the most accurate thermal resistor network for system level thermal evaluation.