André Cardoso

Thermally enhanced FOWLP-development of a Power-eWLB demonstrator

Current Fan Out Wafer Level Packaging (FOWLP) technology, eWLB, has limited heat dissipation capability, as the materials used in, namely the epoxy mold compound (EMC), originally aimed process ability and mechanical stability, but not heat conduction. As eWLB technology expands to WLSiP (Wafer Level System-in-Package) for very high system integration density, combining multiple chips and different components in the same package, the thermal performance becomes a critical factor. In a broader scope, the improvement of its heat dissipation capabilities opens eWLB technology platform also to power applications.

Development of very large Fan-In WLP/ WLCSP for volume production

WLCSP so far was used to enable low-cost manufacturing, and a high performance suitable for low I/O density for mobile and consumer products, wireless connectivity, MEMS and Sensors. Larger dies are usually packaged in Wirebond-BGA or FlipChip-BGA with a small bump pitch, applying underfill material between bumped die and FlipChip substrate to ensure the required board-level reliability. Typical Fan-In WLP/ WLCSP are ranging up to 8mm × 8mm in size, in some extreme cases up to 15mm × 15mm. Limits have been set by the board level reliability of larger chips/ packages, caused by the thermal mismatch between CSP (Chip Scale Package) and PWB (Printed Wiring Board). The paper describes the work done to overcome that limitation and develop, qualify and ramp in volume production a Fan-In WLP/ WLCSP solution beyond common practice. The WLCSP described is one order of magnitude larger in area, something which has never been accomplished in WLCSP before. Package construction and reliability test results will be presented. Daisy Chain Test vehicles have been used with different UBM diameter, UBM design, UBM thickness, dielectric material type, and solder ball alloy variants. All design options achieved minimum costumer requirement at TCoB, the most critical reliability test for such large device. With the right package design and construction, dielectric material and solder ball alloy selection, final product successfully passed more than 900 temperature cycles on board without fails. During the experiments is has been seen that number of cycles until first failure at TCoB and failure mode showed dependency on the above mentioned features.

Fabrication, performance and reliability of a thermally enhanced wafer level fan out demonstrator with integrated heatsink

The leading Fan-Out Wafer-Level Packaging technology, WLFO by NANIUM, stemmed from Infineons embedded Wafer-Level BGA (eWLB) technology, has limited heat dissipation capability, as the materials used in, namely the epoxy mold compound (EMC), originally aimed process ability and mechanical stability, but not heat conduction. As WLFO technology expands to WLSiP (Wafer-Level System-in-Package) for very high-density system integration, the thermal performance becomes a critical factor. In a broader scope, improving heat dissipation capabilities opens WLFO technology platform to power applications. The main challenge for power dissipation on WLSiP packaging is that the EMC must be electrical insulator, placing challenges on both heat conduction and bonding to metallic heat spreader. Whereas mold compounds are typically organic resins filled with inorganic fillers, high performance thermal interface material (TIM) are designed for metal-metal interfaces, not for organic-metal interface as required for chip backside overmolded WLFO package. Another challenge is the assembly of an integrated heatsink, over and larger than the package, on a volume manufacturing capable process, to yield both good thermal conduction and reliable thermomechanical bonding. The work done is part of the collaborative European FP7-ICT project NANOTHERM (Innovative Nano and Micro Technologies for Advanced Thermo and Mechanical Interfaces), together with a consortium of leading IDM, OEM, OSAT, material suppliers and academic/institutes.

Integration of MEMS/Sensors in Fan-Out wafer-level packaging technology based system-in-package (WLSiP)

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/ Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/ Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/ Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/ Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUMs WLFO technology, which is based on Infineons/ Intels eWLB technology, aiming to overcome the current limits for MEMS/ Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/ Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/ Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.

Ultra-Low Temperature FOWLP Process for the Embedding of Low Thermal Budget Sensors and Components Using SU-8 as Dielectric

Fan-Out Wafer Level Packaging (FOWLP) has recently seen a tremendous growth in a broad span of application in telecommunications, automotive and other markets. Its versatility allows its continuous development to accommodate more and more types of components. In light of expanding the technology to include new family of sensors such as MEMS/NEMS, Bio-chips with Microfluidics, magneto-resistive devices and Micro-batteries, the upper limit temperature of FOWLP processing has to be challenged. FOWLP, namely the WLFO technology of NANIUM, based on Infineon/ Intel eWLB technology, is a packaging technology based on wafer reconstitution and RDL processes. The “LTC - low temperature cure” dielectrics used today, are cured at > 200ºC, while solder ball soldering peaks ~260ºC. Despite being considered low temperature, this limit is still not compatible and considered high to a wide range of the new family of sensors targeted to integrate in WLFO. In this work we describe the strategy to lower overall process temperature to

Development of Novel High Density System Integration Solutions in FOWLP-Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages

Expanding FOWLP (Fan-Out Wafer-Level Packaging) from mainly 2D single or multi die solutions to 3D stacked multi-die solutions with SMDs integration, is of crucial importance to meet the requirements arising from new markets such as IoT/IoE and Wearables. This drives the development of new capabilities and technology breakthroughs in the current FOWLP process. One of the most hailed capabilities of FOWLP is the heterogeneous high-density system integration in a package. Wafer Level System-in-Package (WLSiP) already integrates active dies, passive components and even already-packaged components, in a wide range of geometries and materials. Vertical interconnections enable FO-based WL3D solutions, thru Package-on-Package (PoP) assembly. The nature of FOWLP, being a substrate-less technology and using thin-film re-distribution layers, makes the package itself an active interposer. This concept allows very thin packages and PoP solutions, with excellent electrical and thermal behaviour compared to other packaging technologies. To accomplish the vertical package interconnect, or Thru Package Vias (TPV), required for package front to backside connections and 3D assembly, pre-formed vias solution was developed as the concept of choice at NANIUM for lower IO density and package body thickness from 200 to 400um. To allow the process on very thin Fan-Out wafers and, on the last stage, the double side RDL process to complete PoP solution, dedicated Temporary Wafer Bonding (TWB) and Debonding solution for FOWLP were developed and tested. This paper presents the approaches used to effectively enable FOWLP-based WLSIP and WL3D products: Pre-formed via solutions in three build-up options, from process development to reliability result, Wafer front-to-back RDL alignment solutions for high-accuracy 3D package, FOWLP TWB solution for WL3D/ PoP products, and stack-up/ stack-down solution for the final PoP implementation, when there is no space for additional die inside the WLSiP or due to the need to simplify routing complexity and reduce number of RDLs. Several demonstrators are built to demonstrate the above mentioned features, from a very thin,

Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)

The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, ...

Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP

Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to b...

Thin WLFO and based WLSiP enabling WL3D, realized using Temporary Reconstituted Panel Bonding Technology

The interest in FOWLP as new flexible packaging technology platform is continuously increasing. High volume capability is proven for configurations with single die (WLFO), multi-die side-by-side, partially with discrete passives integration (WLMCM and WLSiP), both with single sided single and multiple RDL layers. The next step to achieve higher integration density, e.g. for mobile and IoT applications, is to go in the third dimension (WL3D/WLPoP) with total package thickness below 1mm, targeting 0.8mm and even less in the next development step. High design flexibility, superior performance and small form-factor in x and y, but even more important in z-dimension, are the essential packaging characteristics required for this type of smart system integration. The eWLB based WLFO technology platform of NANIUM promises to deliver all of those requirements. While previous generations of WLFO packages only consisted of one plane of single or multiple RDL layers (frontside RDL at BGA side), recent evolutions enab...

Merging of packaging technologies for highly integrated embedded modules

There is no doubt that component embedding technology becomes more visible in handheld applications like smart phones and wearables. Embedding technology is pushing the miniaturization which is a must for the next big wave of Wearable Electronics and Internet of Things (IoT). The technology is going to System in Package and the question today is how far you can go in miniaturization and how much of complexity and density you can handle. In the frame of the FP7 project UNSETH a new approach is being developed by combining two major packaging technologies to achieve a higher level of miniaturization and to find a cost effective solution for its implementation. The ECP® technology from AT&S and the Fan Out wafer-level packaging (FOWLP) technology from Nanium are the candidates which will be evaluated and further developed to show a system in package (SiP) concept which can handle different components and interconnect complexity in one module. The FOWLP technology provides component in fan out solutions and provides the capability to combine two or more dies in one package to handle ultra-high density interconnection. The ECP® technology is able to package passive, active and FOWLP components in a module construction, which can be used, for example, in security modules. These modules are the target application for the project UNSETH and act as demonstrators for proposed technology merge. This paper will show the development results for test vehicles with embedded FOWLP components. For these components the details of technology, materials and constructions are shown. Different PCB constructions have been manufactured with multilayer constructions up to 16 layers with embedded FOWLP components. Furthermore, the embedding technologies being used and the build-up constructions are another focus of this development. With the progress of UNSETH a lot of reliability investigation has been done and the results are shown in this paper. The basic reliability tests like temperature cycle test, reflow testing and biased HAST have been performed to show the interconnection reliability of these highly integrated modules. An outlook for systems in package with embedded FOWLP based on the technology developed in UNSETH and the potential application will finalize this paper.