Andre K. Nieuwland

C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems

The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologiesenable integration of multiple software programmable processors (e.g., CPUs,DSPs) and dedicated hardware components into a single cost-efficient IC. Ourtop-down design methodology with various abstraction levels helps designingthese ICs in a reasonable amount of time. This methodology starts with a high-levelexecutable specification, and converges towards a silicon implementation.A major task in the design process is to ensure that all components (hardwareand software) communicate with each other correctly. In this article, we tacklethis problem in the context of the signal processing domain in two ways: wepropose a modular, flexible, and scalable heterogeneous multi-processor architecturetemplate based on distributed shared memory, and we present an efficient andtransparent protocol for communication and (re)configuration. The protocolimplementations have been incorporated in libraries, which allows quick traversalof the various abstraction levels, so enabling incremental design. The designdecisions to be taken at each abstraction level are evaluated by means of(co-)simulation. Prototyping is used too, to verify the systems functionalcorrectness. The effectiveness of our approach is illustrated by a designcase of a multi-standard video and image codec.

Exploiting ECC redundancy to minimize crosstalk impact

Signal integrity in high-speed bus designs is put at risk by crosstalk-related-bus delays. This article provides a comprehensive study of the usefulness of error-correcting code (ECC) redundancy in reducing such delays. It shows that dual Rail codes perform better at this task than Hamming codes. We analyze the impact of different ECCs on crosstalk-induced-bus delays (CIBD). We investigate the possibility of exploiting the information redundancy previously necessary to limit CIBD, thus reducing the consequent risk of a systems incorrect operation.

New ECC for crosstalk impact minimization

Signal integrity in high-speed bus designs is put at risk by crosstalk-related bus delays. This article provides a comprehensive study of the usefulness of error correcting code (ECC) redundancy in reducing such delays. It shows that Dual Rail codes perform better at this task than Hamming codes. We describe the modification of DR code that offers some distinct advantages.

Why transition coding for power minimization of on-chip buses does not work

Encoding techniques which minimize the self- or coupling activity of buses are often proposed to reduce power dissipation on system buses. In this paper, we investigate the efficiency of several coding schemes for on-chip buses with respect to overall power dissipation. The power of the codec systems was estimated by power simulations with the lay-outs and related to the savings on the bus. We derived an expression for the energy efficiency of the codecs as a function of bus length (capacitive load). Despite the fact that adaptive schemes could obtain up to 40% savings, the bus lengths required to reduce the overall power consumption are not realistic for on-chip buses.

A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systems

This paper describes the implementation of a data-synchronization scheme that can be used in the functional description and hardware realization of algorithms for heterogeneous multiprocessor architectures. In this scheme, synchronization primitives are chosen such that they can be implemented efficiently in both hardware and software on distributed shared memory architectures, without the need for atomic semaphore instructions. The proposed solution is flexible as the configuration of the data synchronization is programmable even after a hardware realization. It is also scalable since it can be implemented without the need for central resources. We show with experiments that distributed implementations are needed for scalable and high performance systems-on-a-chip.

Soft-Error Rate Testing of Deep-Submicron Integrated Circuits

Soft errors induced by radiation pose a major challenge for the reliability of complex chips processed in state-of-the-art technologies. This paper reviews soft-error rate (SER) characterization by realtime system-SER testing and by accelerated testing. Additionally, we present scaling trends, simulation approaches, and improvement techniques. Special attention is given to soft errors in combinational logic

Coding scheme for low energy consumption fault-tolerant bus

We address the problem of devising the error correcting code which, if used to encode the information on a very deep submicron (VDSM) bus, allows us to achieve fault-tolerance with the minimal impact on bus power consumption and power-delay product. In particular, we first report the results of an analysis that we performed on power dissipation in VDSM fault-tolerant busses using Hamming single error correcting codes. We show that no power saving is possible by choosing between different optimal Hamming codes with the same redundancy. We then propose a new coding scheme which provides a reduction of the energy consumption and power-delay product of over the 11.5% and 45%, respectively, with respect to the optimal (7,4) Hamming code, for a 0.13/spl mu/m CMOS technology bus.

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.

Coding techniques for low switching noise in fault tolerant busses

As device geometries shrink, power supply voltage decreases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is becoming crucial in determining the signal integrity of a system. In this paper we propose ways of merging transition reducing coding techniques with coding techniques for fault tolerant busses (implementing either error detecting codes and error recovery, or correcting codes). In particular, we focus on merging bus-invert code along with the employed error detection or correction coding technique, and show that the maximum number of simultaneous switching drivers can be drastically reduced, thus reducing the SSN and increasing signal integrity. Furthermore, we show how, by properly merging the bus invert encoder and the check bit generator, the latency introduced by the proposed coding techniques can be minimized and the number of additional wires can be kept minimal.

Power consumption of fault tolerant codes: the active elements

On-chip global interconnections in very deep submicron technology (VDSM) ICs are becoming more sensitive and prone to errors caused by power supply noise, crosstalk noise, delay variations and transient faults. Error correcting codes can be employed in order to provide signal transmission with the necessary data integrity. We compared Dual Rail encoding versus Hamming with respect to power consumption of the bus wires themselves (passive capacity model) [Rossi et al., 2002]. In this paper we analyze the contribution of the active elements of both coding schemes. We first present a detailed analysis of the power consumption of an encoded bus, taking into account the bus wires (with mutual capacitances, drivers, repeaters and receivers), as well as the encoding/decoding circuitry. Then we compare the two considered coding technique with respect to the power consumption, and we show how different tradeoffs can be achieved. Our analysis is based on a realistic bus structure, implemented in a 0.13/spl mu/m CMOS technology.