Daniele Rossi

Latch Susceptibility to Transient Faults and New Hardening Approach

In this paper, we analyze the conditions making transient faults (TFs) affecting the nodes of conventional latch structures generate output soft errors (SEs). We investigate the susceptibility to TFs of all latch nodes and identify the most critical one(s). We show that, for standard latches using back-to-back inverters for their positive feedback, the internal nodes within their feedback path are the most critical. Such nodes will be hereafter referred to as internal feedback nodes. Based on this analysis, we first propose a low-cost hardened latch that, compared to alternative hardened solutions, is able to completely filter out TFs affecting its internal feedback nodes while presenting a lower susceptibility to TFs on the other internal nodes. This is achieved at the cost of a reduced robustness to TFs affecting the output node. To overcome this possible limitation (especially for systems for high-reliability applications), we propose another version of our latch that, at the cost of a small area and power consumption increase compared to our first solution, also improves the robustness of the output node, which can be higher than that of alternative hardened solutions. Additionally, both proposed latches present a comparable or higher robustness of the input node than alternative solutions and provide a lower or comparable power-delay product and area overhead than classical implementations and alternative hardened solutions.

A model for transient fault propagation in combinatorial logic

Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.

Multiple transient faults in logic: an issue for next generation ICs?

In this paper, we first evaluate whether or not a multiple transient fault (multiple TF) generated by the hit of a single cosmic ray neutron can give rise to a bidirectional error at the circuit output (that is an error in which all erroneous bits are 1s rather than 0s, or vice versa, within the same word, but not both). By means of electrical level simulations, we show that this can be the case. Then, we present a software tool that we have developed in order to evaluate the likelihood of occurrence of such bidirectional errors for very deep submicron (VDSM) ICs. The application of this tool to benchmark circuits has proven that such a probability can not be neglected for several benchmark circuits. Finally, we evaluate the behavior of conventional self-checking circuits (generally designed accounting only for single TFs) with respect to such events. We show that the modifications generally introduced to their functional blocks in order to avoid output bidirectional errors due to single TFs (as required when an AUED code is implemented) can significantly reduce (up to the 40%) also the probability to have bidirectional errors because of multiple TFs.

Modeling Crosstalk Effects in CNT Bus Architectures

Carbon nanotubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, issues associated with crosstalk among bus lines implemented by CNTs are investigated in detail. CNT-based interconnects are modeled and the effects of crosstalk on performance and correct operation are evaluated by simulation. Existing models are modified to account for geometries in bus architectures made of parallel single-walled nanotubes and a single multiwalled nanotube. New RLC equivalent circuits are proposed for these bus architectures. A novel bus architecture with low crosstalk features is also proposed. This bus architecture is made of dual-walled nanotubes arranged in parallel. In this architecture, the crosstalk-induced delay and corresponding uncertainty (as well as crosstalk-induced peak voltage) are significantly reduced; a modest area penalty is incurred. Reductions up to 59% for the crosstalk-induced delay and up to 81% for the crosstalk-induced peak voltage are reported. These results confirm that the proposed bus arrangement noticeably improves performance and provides reliable operation

Novel transient fault hardened static latch

University of Bologna

Configurable Error Control Scheme for NoC Signal Integrity

In this paper we propose a novel error control scheme to cope with errors affecting the communication links of a NoC. Our scheme can be configured in correction mode, detection mode, and mixed mode, depending on the particular application, thus allowing to meet different quality of service (QoS) levels in terms of error control. For each configuration mode, we propose different error control policies and we consider SEC hamming codes SEC/DED Hsiao codes, and symbol error correcting codes. We evaluate advantages and drawbacks of each approach, in terms of signal integrity, area overhead and impact on performance.

New ECC for crosstalk impact minimization

Signal integrity in high-speed bus designs is put at risk by crosstalk-related bus delays. This article provides a comprehensive study of the usefulness of error correcting code (ECC) redundancy in reducing such delays. It shows that Dual Rail codes perform better at this task than Hamming codes. We describe the modification of DR code that offers some distinct advantages.

High-Performance Robust Latches

First, a new high-performance robust latch (referred to as HiPeR latch) is presented that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good trade-offs in terms of performance, robustness, and cost, our proposed latches are particularly suitable to be adopted on critical paths.

Error correcting code analysis for cache memory high reliability and performance

In this paper we address the issue of improving ECC correction ability beyond that provided by the standard SEC/DED Hsiao code. We analyze the impact of the standard SEC/DED Hsiao ECC and for several double error correcting (DEC) codes on area overhead and cache memory access time for different codeword sizes and code-segment sizes, as well as their correction ability as a function of codeword/code-segment sizes. We show the different trade-offs that can be achieved in terms of impact on area overhead, performance and correction ability, thus giving insight to designers for the selection of the optimal ECC and codeword organization/code-segment size for a given application.

Low Cost NBTI Degradation Detection and Masking Approaches

Performance degradation of integrated circuits due to aging effects, such as Negative Bias Temperature Instability (NBTI), is becoming a great concern for current and future CMOS technology. In this paper, we propose two monitoring and masking approaches that detect late transitions due to NBTI degradation in the combinational part of critical data paths and guarantee the correctness of the provided output data by adapting the clock frequency. Compared to recently proposed alternative solutions, one of our approaches (denoted as Low Area and Power (LAP) approach) requires lower area overhead and lower, or comparable, power consumption, while exhibiting the same impact on system performance, while the other proposed approach (denoted as High Performance (HP) approach) allows us to reduce the impact on system performance, at the cost of some increase in area and power consumption.