Atul Katoch

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

From 90 nm and below, SoC integration is reaching the point where it makes technical and economic sense to integrate embedded DRAM (eDRAM) onto a die. While eDRAMs have 2.5x to 4x density compared to SRAMs and have lower soft-error rate they are slower in operation. In a conventional DRAM with a single column access device for read and write, a write operation is started only after the bitline sense amplifiers are turned on and the bitlines are well on their way to full restoration. This is to avoid destroying data due to premature access to global bitlines in the non-writing columns. This delay in the write operation increases row cycle time to allow the storage node to be fully written. Accelerating write cycle with early access only in the required columns requires a large area penalty because local sense amplifiers in one bank are usually grouped into a large block where all control signals are shared. Also an embedded DRAM in a standard 65 nm twin-tub SOI CMOS process that uses a local sense amplifier with VDD sensing and separate ports for read and write, with these operations synchronized with sensing is described. This eDRAM speeds up the row cycle with low area overhead by reducing the number of signals to control the ports and making write and read operations indistinguishable at the bank level.

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications

Mobile applications, such as smartphones streaming HD videos or virtual-reality headsets rendering 3D landscapes, need SRAM memories that can be put in a low-power state to extend battery life, but can also offer high performance operation when required [1]. This paper will merge a 10nm technology with a dual-rail SRAM architecture to achieve superior power savings and performance scaling in comparison to the previous 16nm technology node [2]. Due to its simple design and area efficient layout, the 6T SRAM bitcell continues to be the primary memory technology used in almost all SoC and processor designs in high volume manufacturing today. The 10nm technology uses low-leakage, high-performance, second-generation FinFET transistors; it also offers a 6T cell (0.042µm2), for area and power savings, that does not require read or write assist circuits to achieve low voltage (Vmin) operation. This bitcell uses a fin ratio of 1∶2∶2 (PU:PG:PD), as illustrated in Fig. 12.3.1.