Andrea Cappelli

XiSystem: a XiRisc-based SoC with a reconfigurable IO module

In the nanometer era, the increase in nonrecurring engineering costs is a challenge for SoCs that can be faced through a standardization process. Hardware specialization of a standard platform to a given application can be achieved by exploiting reconfigurable technology. This paper presents a XiSystem SoC, which integrates two different field-programmable devices to provide application-specific computing blocks and IOs. A XiRisc reconfigurable processor is exploited to achieve more than one order of magnitude speed-up and energy consumption reduction vis-a/spl grave/-vis a DSP-like processor, while an eFPGA is integrated in the system in order to make it flexible enough to support various IO ports and protocols. The reconfigurable IO device is also utilized for pre/post data processing and implementation of some standard computational blocks.

A dataflow control unit for C-to-configurable pipelines compilation flow

In the field of embedded systems, reconfigurable processors, composed of a standard processor core coupled with a reconfigurable device, are gaining more and more importance. Algorithm developers are facing the issue of mapping applications on configurable hardware, without a specific knowledge of the underlying architecture. In this paper, we present a modular data flow control unit for a reconfigurable datapath, which can be easily programmed starting from the C description of the required functionality.

A Multi-Context Pipelined Array for Embedded Systems

The integration of a reconfigurable device into complex SoCs is a common request aimed at adding software programmable efficient computational blocks to a system. In such environment a traditional approach in FPGA design could not meet the need for an easy-to-use and easy-to-integrate device. This paper presents the PiCoGA-II reconfigurable datapath which has been designed as a multi-context array to provide fast dynamic reconfiguration. Architectural choices to reduce the area overhead of this approach are described. A reconfigurable dedicated control unit provides a clear interface for an easy integration of the device together with a hardware support for a programming Mow starting from a sequential high-level language. The logic cells have been redesigned with respect to the previous version, to improve their computational efficiency and flexibility. The PiCoGA-II has been fabricated in 0.13mum CMOS technology. The implementation of several MPEG-2 kernels shows that the multi-context array has a computational density which is 2times higher than an equivalent single-context one and is 2times higher than a Virtex-II FPGA when all the 4 contexts are utilized

A reconfigurable processor architecture and software development environment for embedded systems

Flexibility, high computing power and low energy consumption are strong guidelines when designing new generation embedded processors. Traditional architectures are no longer suitable to provide a good compromise among these contradictory implementation requirements. In this paper we present a new reconfigurable processor that tightly couples a VLIW architecture with a configurable unit implementing an additional configurable pipeline. A software development environment is also introduced providing a user-friendly tool for application development and performance simulation. Finally, we show that the HW/SW reconfigurable platform proposed achieves dramatic improvement in both speed and energy consumption on signal processing computation kernels.

An embedded reconfigurable datapath for SoC

In this paper we present the new version of a multi-context reconfigurable datapath called PiCoGA (pipelined configurable gate array). The device provides a clear interface model and can be easily embedded in SoC systems where low power consumption and high computation capability are required. New logic cells and routing architecture have been designed for an efficient implementation of computation-intensive algorithms. The integration of a dedicated control unit for pipeline activity control provides a dataflow computational model which is easy to be integrated in a SoC. The embedded datapath has been designed using a 0.13 /spl mu/m CMOS technology. The implementation of several functions in the datapath achieves an average gate density of 1.3 KGates/mm/sup 2/ for each of the four available contexts.

Decoder-based multi-context interconnect architecture

Multi-context FPGAs are a convenient solution for run-time reconfiguration, but they suffer from large area occupation. This is mainly due to programmable interconnect configuration memories which need to be replicated as many times as the number of contexts. To overcome this limitation a new decoder-based interconnect architecture is proposed. Dramatic improvements in terms of area and delay with respect to previous approaches are presented, such that multi-context FPGAs can finally become a viable solution for next generation configurable devices.