Andrea Gerosa

A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers

A fully integrated differential low-power low-noise amplifier (LNA) for ultrawideband (UWB) systems operating in the 3-5-GHz frequency range is presented. A two-section LC ladder input network is exploited to achieve excellent input match in a wideband fashion and to optimize the noise performance. Prototypes fabricated in a digital 0.13-mum complementary metal oxide semiconductor technology show the following performance: 9.5-dB peak power gain, 3.5-dB minimum noise figure, -6-dBm input-referred 1-dB compression point, and -0.8-dBm input-referred third-order intercept point, while drawing 11mA from a 1.5-V supply. The realized LNA is compared with previously reported LNAs tailored for the same frequency range

Transformer-Based Dual-Mode Voltage-Controlled Oscillators

In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-mum CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration

Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems

A 0.13-mu m CMOS fourth-order notch filter for the rejection of the 5-6 GHz interference in UWB front-ends is reported. The filter is integrated into an analog front-end for Mode #1 UWB. A thorough analysis based on a simplified model of the filter is carried out. An algorithm for the automatic tuning and calibration of the filter is also discussed and demonstrated. Two versions of the circuit are designed and fabricated: the first comprises a low-noise amplifier and the filter, and the second expands it to a complete front-end. In the latter version the filter was also redesigned. The filter provides more than 35 dB of attenuation and has a tuning range of 900 MHz, adding less than 30% power consumption to the LNA. The out-of-band IIP3 (higher than -13.2 dBm with the filter off) takes a 9-dB advantage from the filter and the compression of the gain due to the out-of-band blocker is reduced by at least 6 dB in the complete front-end. The conversion gain of the front-end is 25 dB per channel, its average noise figure is lower than 6.2 dB, and its in-band 1-dB compression point is higher than - 30 dBm at a power consumption of 32 mW.

A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-/spl mu/m CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).

An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers

This study proposes an energy detector for a noncoherent impulse-radio UWB receiver, designed in a 0.18-mum CMOS technology. The squaring functionality is realized exploiting the quadratic characteristic of MOS transistors, and the deviation from such a characteristic due to short channel effects and device mismatch is carefully considered in the paper. The squared signal is integrated using a Gm-C integrator that is interfaced with the squarer using a flipped voltage follower current sensor as a current to voltage converter. The proposed circuit dissipates 5.4 mW for a receiver sensitivity at the antenna of -89 dBm. Synchronization is demonstrated at the system level and some considerations on robustness to narrowband interferers are presented.

A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13

This paper presents a fully integrated UWB-IR transceiver front-end operating in the 7.25-8.5 GHz band designed for high overall transmission and detection energy efficiency and robustness to interferers. The transceiver front-end features a pulsed transmitter that wakes up when triggered by a digital signal, generates a pulse, and automatically switches-off in less than 2 ns. The receiver includes an LNA, a VGA, a squarer, a windowed integrator, and a comparator to perform PPM demodulation of the data. A prototype of the transceiver front-end was integrated in a 0.13 μm CMOS technology. The transmitter delivers 13 pJ/pulse to the antenna consuming about 190 pJ/b, with an efficiency ηT=7%, well in excess of comparable designs. Using pulse polarity scrambling, it complies with the FCC spectral emission limits up to a pulse repetition frequency (PRF) of 5 MHz. The receiver achieves a sensitivity of -87 dBm at a PRF of 100 kHz, and of -70 dBm at a PRF of 5 MHz, while consuming 4.2 mW. It can tolerate interferers up to -12 dBm at 5.4 GHz.

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In this work, a dual-mode oscillator built around a transformer-based resonator is proposed. By making use of this technique, a wideband VCO is designed that features a 69% tuning range spanning from 3.4 GHz to 7 GHz. An excellent 14.8 dB power-frequency-tuning-normalized figure of merit, accounting of -118.6 dBc/Hz phase noise at 1 MHz offset from the 4.6 GHz carrier at 1 mW power consumption, is reported

CMOS

This work proposes a random numbers generator for application in the field of secure communications. In order to get truly unpredictable sequences a chaotic system is used. Indeed, due to their extreme sensitivity to initial conditions, chaotic systems lend themselves to be exploited for generation of random numbers. This work explores this possibility: particularly an efficient architecture, based on a pipeline analog-to-digital converter, has been singled out, in order to realize a simple circuit arrangement of the number generator. According to simulation results, the circuit provides sequences of 8-b numbers that are uniformly distributed and statistically independent, at a rate of 20 Ms/s. The circuit is realized in 0.8-/spl mu/m CMOS technology, and dissipates 50 mW.

A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO

GSM-compliant local oscillator consuming a tiny die area of only 0.06 mm and drawing 9 mA from a 1.2 V supply has been designed in a 65 nm CMOS process using thin-oxide devices only. The system is made of a 13 to 15 GHz LC VCO followed by a divide-by-four injection-locked frequency divider. The divider employs a ring oscillator-based topology leading to a two octave locking range with limited area and power consumption. The phase noise at the output of the divider is below -133 dBc/Hz at 3 MHz offset over the tuning range.

A fully integrated chaotic system for the generation of truly random numbers

Sub-harmonic injection locking is employed to generate the fast-hopping carriers required in UWB systems for WiMedia . A very small area 90-nm CMOS prototype synthesizes the frequencies of band group #6 with a hop time shorter than 4 ns . It occupies 0.074 mm2 and draws 30 mA from a 1.2 V supply. Phase noise at 8.71 GHz is -112 dBc/Hz at 1 MHz offset. The design is supported by a thorough analysis that emphasizes the tradeoffs in the parameters of the proposed system.