Daniele Vogrig

A 0.35-/spl mu/m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-/spl mu/m CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).

An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers

This study proposes an energy detector for a noncoherent impulse-radio UWB receiver, designed in a 0.18-mum CMOS technology. The squaring functionality is realized exploiting the quadratic characteristic of MOS transistors, and the deviation from such a characteristic due to short channel effects and device mismatch is carefully considered in the paper. The squared signal is integrated using a Gm-C integrator that is interfaced with the squarer using a flipped voltage follower current sensor as a current to voltage converter. The proposed circuit dissipates 5.4 mW for a receiver sensitivity at the antenna of -89 dBm. Synchronization is demonstrated at the system level and some considerations on robustness to narrowband interferers are presented.

A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13

This paper presents a fully integrated UWB-IR transceiver front-end operating in the 7.25-8.5 GHz band designed for high overall transmission and detection energy efficiency and robustness to interferers. The transceiver front-end features a pulsed transmitter that wakes up when triggered by a digital signal, generates a pulse, and automatically switches-off in less than 2 ns. The receiver includes an LNA, a VGA, a squarer, a windowed integrator, and a comparator to perform PPM demodulation of the data. A prototype of the transceiver front-end was integrated in a 0.13 μm CMOS technology. The transmitter delivers 13 pJ/pulse to the antenna consuming about 190 pJ/b, with an efficiency ηT=7%, well in excess of comparable designs. Using pulse polarity scrambling, it complies with the FCC spectral emission limits up to a pulse repetition frequency (PRF) of 5 MHz. The receiver achieves a sensitivity of -87 dBm at a PRF of 100 kHz, and of -70 dBm at a PRF of 5 MHz, while consuming 4.2 mW. It can tolerate interferers up to -12 dBm at 5.4 GHz.

\mu{\hbox{m}}

This study proposes an energy detector for a noncoherent impulse-radio UWB receiver, designed in a 0.18-mum CMOS technology. The squaring functionality is realized exploiting the quadratic characteristic of MOS transistors, and the deviation from such a characteristic due to short channel effects and device mismatch is carefully considered in the paper. The squared signal is integrated using a Gm-C integrator that is interfaced with the squarer using a flipped voltage follower current sensor as a current to voltage converter. The proposed circuit dissipates 5.4 mW for a receiver sensitivity at the antenna of -89 dBm. Synchronization is demonstrated at the system level and some considerations on robustness to narrowband interferers are presented.

CMOS

In this work we present a full analog turbo decoder for hard-disk EPR-IV read channels in CMOS technology. The design is based on a current-mode approach developed by Loeliger et al. [2001], for the analog implementation of sum-product algorithms. The circuits main attractions are the coding gain offered by turbo codes over the uncoded EPR-IV channel, and the relative simplicity and power efficiency of the analog approach over the digital approach. The circuit is developed in a 0.18 /spl mu/m CMOS technology and operates at a 1.8 V power supply, with a total simulated power consumption (including peripheral circuitry) of about 650 mW at 400 Mb/s.

An energy-detector for non-coherent impulse-radio UWB receivers

The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels

In this paper, we present an all-analog implementation of the rate-1/3, block length 40, universal mobile telecommunications system (UMTS) turbo decoder. The prototype was designed and fabricated in 0.35 μm complementary metal-oxide-semiconductor technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast bit-error rate simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-1/3 analog turbo decoder for UMTS defined in the Third Generation Partnership Project standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

An analog turbo decoder for the UMTS standard

The increasing interest in impulse radio UWB communication links focuses the research interest on building blocks optimized for these specific systems. In this context, this paper proposes a ring oscillator for an impulse radio UWB transmitter. A multiloop ring oscillator is considered because it holds the potential of both high oscillation frequency and fast switch-on time. The novelty of the proposed inverter cell is found in the possibility to adjust the oscillation frequency digitally, rather than with an analog voltage. This leads to larger tuning range and less sensitivity to control noise. The digitally controlled oscillator is designed in 0.13µm CMOS technology and according to simulations the tuning range is from 4 GHz to 12.5 GHz. The power consumption is below 8 mW.

Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code

In this paper, the design of a fully analog iterative decoder for a serially concatenated convolutional code is presented. The decoder is reconfigurable in both block length and code rate. An interleaver size up to 2400 bit is considered. The decoder core implements a single SISO working on a window of the whole code trellis. It is then reused several times to decode the two constituent codes. The resulting decoder performs iterations, but it is fully analog. The extrinsic information exchanged in the decoding process is stored in an analog memory and permuted through a reconfigurable interleaver. Behavioral analysis of the decoder as well as precision and mismatch impact on performance are reported in the paper.

A digitally programmable ring oscillator in the UWB range

This paper presents an ultra-wideband impulse radio (UWB-IR) receiver (RX) for ultralow energy consumption applications. The design of the receiver takes full advantage of the pulsed nature of UWB-IR communication technology aiming at architectural simplicity, avoidance of precise frequency reference generation, and symbol-level duty-cycled operation. The tradeoff between receiver sensitivity and energy-per-bit consumption is briefly addressed for the different design options taken into consideration. A prototype of the receiver was fabricated in 130-nm CMOS technology and tested. The testing results show that the receiver supports a 4.4-Mb/s data rate, with a sensitivity of 0.57 aJ. Thanks to symbol-level duty-cycling and architecture and circuit optimization, such an outstanding performance is attained at an energy consumption of only 440 pJ/b. The receiver robustness against narrowband interferers is also assessed by measuring the blocker power required to degrade the receiver sensitivity by 1 dB: measurement shows a blocker power level that increases from −45 dBm at 6 GHz up to 3 dBm at 2.4 GHz.