Andrea Molino

FPGA implementation of time-frequency analysis algorithms for laser welding monitoring

The on-line monitoring and detection of defects in laser welding is a basic manufacturing requirement in several applicative contexts, as vehicle assembly in automotive production. This work presents the FPGA implementation of time-frequency analysis algorithms as an effective solution compared with pure software implementation based on different modern processors. In particular the proposed FPGA based approach not only satisfies the processing constraints of the considered application, but still offers a high degree of flexibility and modularity.

DSP implmentation of a low complexity motion detection algorithm

The use of video cameras for video surveil- lance and monitoring has always been very important, but nowadays, due to the need to fight terrorism and crime, a real explosion in the use of technological devices such as web cams and hidden cameras is taking place. In this work we investigate a low-complexity motion detection algorithm recently proposed in the literature. Starting from the algorithm itself, the aim of this paper is twofold: to improve the existing work making it robust against illumination changes, and to port the proposed solution on a DSP board.

Reconfigurable and low power 2D-DCT IP for ubiquitous multimedia streaming

An energy efficient architecture for the discrete cosine transform is presented. The proposed IP is intended to be used as the transform stage in a mobile H.263 codec. In particular, it seems well suited for an FPGA implementation since, after a complete place and route process, it is able to sustain a full-motion PAL video streaming operating at a frequency of 74 MHz with a dynamic power dissipation of just 39 mW.

Evaluation of a FFT-Based Acquisition in Real Time Hardware and Software GNSS Receivers

The first step of the digital processing within a Global Navigation Satellite System (GNSS) receiver is the signal acquisition. The receiver has to detect the satellites in view, and for each of them, has to estimate the Doppler shift and the code phase of the received signal. In order to speed up the acquisition process, modern receivers use fast acquisition technique based on the fast Fourier transform (FFT). This paper presents the complexity evaluation of a FFT-based acquisition technique, suitable for new GNSS signals and for both software and hardware implementations. After the description of the algorithm, the focus will be on the comparison of the results obtained with a Xilinx FPGA board and a software receiver implemented on a general-purpose processor.

FPGA system-on-chip soft IP design: a reconfigurable DSP

In this paper a novel architecture for a scalable DSP core is proposed. Due to the increase of system resources available on last generation FPGA, the System-on-Chip paradigm can be borrowed from classical silicon implementations into reconfigurable environments. Presently, off-the-shelf devices suffer the need for remarkable static power consumption: however it is forecastable that technology improvements will extend FPGA usage to mobile systems. Despite the increasing importance gathered by reconfigurable computing, a lack of retargetable soft-processor IP is felt. In particular, this IP aims to fill the existing gap between specific coprocessor units and general purpose soft cores. The proposed architecture exhibits interesting figures both in terms of area occupation as well as maximum operative clock frequency. In order to validate the system performance, some common telecommunication algorithms have been mapped on the DSP. Good experimental results have been obtained running at 89 MHz on a XILINX XCV1000.

Parametric FPGA early-late DLL implementation for a UMTS receiver

Third generation communication schemes, mainly based on the W-CDMA access technique, are replacing second generation ones both in the US and in EU countries. CDMA makes possible simultaneous communications, spreading the users information over a large frequency range by means of orthogonal codes. One of the main problems of this type of communication is the need for exact alignment between the received sequence and the locally despreading code. The early-late block is devoted to maintaining this alignment using a delay locked loop, provided that the first alignment is performed by the synchronizer block. A reconfigurable early-late tracking loop architecture, for SDR (software defined radio) implementation, is proposed. Very promising results have been obtained from logical synthesis and from physical implementation on a Xilinx XCV100E (48.7 Mhz, 616 FFs, 719 LUTs).

A reconfigurable, power-scalable rake receiver IP for W-CDMA

During the last years wireless market has experienced an exponential growth. 2G systems are essentially voice-oriented: the main innovation expected from 3G ones is the ubiquitous Internet and multimedia fruition. The transition from 2G to 3G provides both opportunities and challenges: one way to make this migration as smoother as possible relies on the employment of reconfigurable architectures. In this paper a reconfigurable Rake Receiver for W-CDMA is proposed. Very promising results from the physical implementation on a XCV300E have been obtained.

Multimedia SoC: a systolic core for embedded DCT evaluation

The growing interest in video standards has fostered many research activities towards efficient transform architectures. Many works have been proposed concerning the discrete cosine transform (DCT); however the need is felt for efficient cores, ready to be embedded into systems on chip (SoC). To grant maximal interoperability among different cores, the proposed DCT one has been designed to be wishbone compliant. A reconfigurable systolic 2D-DCT architecture is proposed and physical implementation results on XILINX Virtex-E FPGA are given. As far as performance is concerned, this core is able to process 128 XGA (1024/spl times/768) frames/s running at 110 MHz.

FPGA digital down converter IP for SDR terminals

During the past years, software platforms have proved a superior scalability with respect to hardware solutions. However, wireless communication rates can not be faced resorting only to software. Software defined radio paradigm will try to push reconfigurable blocks as near as possible to the antenna. The first block suitable in this implementation is the digital down converter, needed to adapt higher antennas data rate to intermediate frequency ones. In this paper a fully reconfigurable IP of a cascaded integrator comb (CIC) filter, an economical class of multiplier-less filters, is proposed. FPGA implementation has lead to very satisfactory results: 135 MHz on a XCV100E.

Optimized CORDIC core for frequency-domain motion estimation

This paper describes a CORDIC-based architecture to efficiently compute the phase difference between two complex numbers. The problem of fast phase difference computation is central in many signal processing algorithms. Our main focus has been posed on the phase correlation technique applied to motion estimation. A reduced complexity solution is proposed and specifically tailored to suit the application needs. The presented algorithm has been completely implemented in 0.25 /spl mu/m standard-cell CMOS technology. As far as the performance are concerned the designed core outperforms a recently designed solution by more than 50% under area and energy standpoints.