G. Piccinini

Technology for ATM multigigabit/s switches

It is generally accepted that the reasons for selecting ATM as the switching and multiplexing method for B-ISDN are the advantages the bandwidth on demand philosophy offers: flexibility and statistical gain. The main benefit of the throughput improvement that is possible to achieve with link rates of Gb/s in ATM is the exploitation of statistical gain with bursty high peak rate sources. But not only statistical gain justifies the necessity for such advanced technology. High speed ATM switching systems take advantage of the reduction of the number of interface devices (due to multiplexing) and also the number of stages in the ATM switching network, obtaining better figures in the cost/performance ratio. This paper describes an ATM switch that exploits parallelism and segmentation to perform very high speed ATM switching. With this characteristic it is possible to switch more than 2.5 Gb/s per input/output using CMOS and BiCMOS technologies (present implementation) and beyond with more advanced BiCMOS/GaAs.

A CMOS power-delay model for CAD optimization tools

The need of fast and reliable models for CMOS gates has grown in importance not only for the simulation of digital VLSI circuits, but also for their optimization. In a library based design the optimum of speed is a basic step to achieve high performance, but also power consumption must be considered with increasing care. A simultaneous power-delay evaluation can be performed using a new model developed for sub-micron CMOS technologies, allowing better multi-objective optimization.

Computationally Efficient Multiple-Independent-Gate Device Model

Nanowire field effect transistors (FETs) with multiple independent gates around a silicon channel feature ultimate gate control, and are regarded as promising candidates for next-generation transistors. Being inherently more complex than the conventional gate-all-around nanowire FETs, they require longer simulation time, especially with numerical simulations. We present a new model, enabling the efficient computation of voltages and current in modular semiconductor structures with an arbitrary number of independent gate regions. Its validity extends on gate-all-around MOSFETs, FinFETs, and gateless channels. It exploits existing models for conventional devices and builds results on top of these. Being completely general, the method is independent from the models used to describe each region, a charge-based model in our case. Applied to a multiindependent-gate nanowire FET structure, extensive comparison of the proposed method with results from physics-based TCAD Atlas software and with numerical exact results show very good agreement with relative errors of less than 1.8% for potentials and less than 4% for currents, under a broad variations of physical parameters as well as biasing conditions. Interpreted language implementation shows a performance advantage in excess of one order of magnitude with respect to standard optimized numerical methods, still providing excellent accuracy, and making it suitable for implementation in circuit simulators.

Accurate technology independent models for submicron CMOS and BiCMOS circuits

Two accurate analytical models for the delay evaluation of submicron CMOS and BiCMOS buffers are presented. They are technology independent in the way that they base their validity on a set of process parameters that can be extracted directly from SPICE models or experimental measurements. Both models make use of an accurate delay model for submicron MOS transistors which is presented too. It takes into account a ramp shape input voltage and a feed-forward capacitive coupling between gate and drain contacts, along with the main second order effect present in submicron MOS transistors. Though the calculations are carried out for a buffer case, the models can be applied to the delay study of more general circuits (e.g. for the optimization of high speed logic gates).