Andrea Simonetti

Analysis of data dependence of leakage current in CMOS cryptographic hardware

A novel power analysis technique for CMOS cryptographic hardware based on leakage power consumption measurements is presented. Algorithms and models to predict the input vector for maximum and minimum leakage currentallin CMOS gates are reviewed. Extensive transistor level simulations on a simple CMOS crypto core are presented. Leakage current measurements carried out on an ASIC for cryptographic applications implemented in a 0.13 um CMOS technology are reported. The results of this work show that leakage current can be exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware implemented in short channel CMOS technologies.

Switched Capacitor Sample-and-Hold Circuit with Input Signal Range beyond Supply Voltage

A switched capacitor sample-and-hold (S/H) circuit with extended dynamic range beyond the supply voltage is presented. The proposed architecture includes a gate-bootstrapped circuit and an improved flip-around S/H with two selectable configurations. Simulations in a 0.13 ¿m CMOS technology show that the new system is capable of sampling a below-ground signal and allows an interface adapter that enhances the dynamic range of the low-voltage analog-to-digital (A/D) converters without affecting the input bandwidth.

A measurement technique for the vibrating wire sensors

Wireless sensor networks are becoming a reality in civil engineering. Various features as the low cost, feasibility of being supplied by energy harvesting techniques such as a low maintenance, make wireless sensor nodes a very attractive solution when compared to wired processing units. Vibrating wire strain gauges are a particular class of force transducers very simple to embed in reinforced concrete. Nevertheless, an optimal control of these sensors for the low-power applications, requires a dedicated measurement principle that differs from the proven techniques. In this work, we propose a strain measurement based on the RMS value of the harmonic response. Theoretical calculations and experimental results are also given to demonstrate its validity.

Near-optimum switched capacitor sample-and-hold circuit

Performance of the low-voltage and power-efficient analog-to-digital (A/D) converters, like cyclic and pipeline topologies, can be significantly enhanced by using advanced analog cores. This paper describes a careful switched capacitor (SC) architecture that can be used as a simple low-voltage implementation of the flip-around sample-and-hold (S/H) circuit. The S/H has been simulated in a 0.13µm CMOS technology featuring a signal to noise and distortion ratio (SNDR) of −75dB at 12Ms/s for a 1Vpp output voltage. Theoretical calculations and experimental results are also given to demonstrate its validity.

A low-power sample-and-hold circuit based on a switched-opamp technique

A novel low-power and high-performance sample-and-hold (S/H) front-end suitable for pipelined and cyclic analog-to-digital converters using 0.25-mum CMOS technology is proposed. This sampler uses a new S/H architecture exploiting a switched telescopic cascode operational transconductance amplifier (OTA) to minimize power consumption. Simulation results show that the proposed solution allows simple and reliable S/H function and an effective power reduction without noise and distortion penalty.

A sample-and-hold circuit with very low gain error for time interleaving applications

A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.

On practical second-order power analysis attacks for block ciphers

We propose a variant for a published second-order power analysis attack [1] on a software masked implementation of AES-128 [2]. Our approach can, with reduced complexity, produce the same result as the original one, without requiring any additional tool. The validity of the proposed variant is confirmed by experiments, whose results allow for a comparison between the two approaches.

Fast Multi-Channel Driver for High-Voltage Micromirrors Switches

The most popular micromirrors switches, work with a sinusoidal low-frequency carrier obtained by a simple generator with a rude shift-level circuitry. Aiming to the problem for the pulsed rectangulars carrier signals, more and more used in the digital and scanning bonded silicon mirrors, the analog amplifiers arranged to operate in a saturation region, decrease the sharpness of leading and trailing edges of a rectangular pulse envelope (i.e. audio amplifiers). This approach makes unusable a set of features of these actuators. The well-known systems, based on high-voltage logic ports, capable of resulting an output carrier that having the shape substantially a square waveform, require large current and are very expensive. In the proposed architecture, it is possible to reduce both the excessive and unnecessary spectral components resulting from the rapid rise and fall time of the rectangular envelope as also relax the current requirements with a dedicated circuitry arrangement that modifies the output source in a trapezoidal envelope. A new scheme for decreasing power requirements using a source degenerated logic port is introduced. This method, addresses these issues by tracking the output current with a very simple approach that doesn’t require an additional consumption as most solutions do.

Differential Capacitance Analysis

This paper proposes a new kind of side-channel attack where the correlation between processed data and total capacitance seen looking into the power supply pin of a cryptographic device is exploited. The attack is introduced and advantages and drawbacks with respect to the well-known power analysis are discussed. The attack implementation and experimental results attacking a static CMOS implementation of a 8051 microprocessor core are provided and a comparison between the proposed technique and power analysis is carried out. The obtained results are promising and future activities are planned to assess the performance of this new side-channel analysis when attacking secure implementations.