Francesco Centurelli

Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band.

Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies

Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4- VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches.

Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters

In this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a 0.13-μm CMOS technology show an accuracy of the model as high as 17 bits.

Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters

We propose an algorithm for the digital background calibration of time-interleaved analog-to-digital converters (ADCs), which is capable of accurately calibrating errors due to offset, gain, and timing mismatches, as well as nonlinearities due to errors in the channel ADCs. Calibration is performed in the background without interrupting data conversion, even in the presence of wideband input signals and signals beyond the first Nyquist band. The proposed algorithm improves a previous work by the authors by allowing higher precision, particularly in the case of many interleaved channels and large mismatches. Accuracy improves by 3–8 bits with respect to the previous algorithm and up to 10 bits with respect to the uncalibrated case.

A class-AB flipped voltage follower output stage

In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage low-power stages requiring low bias currents but driving large capacitive loads with large signal swing. These buffers have been compared using 65nm CMOS technology models provided by STMicroelectronics. The buffer consumes 10µA from a 1.2V supply, and has a bandwidth of 100MHz with a 2pF load. It has −50dB HD2 and −60dB HD3 when the input is a 0.5VPP sinusoid at 1MHz, and the 1% settling time to a 0.5VPP square wave is about 20ns.

CMOS High-CMRR Current Output Stages

Two CMOS current output stages are presented. Compared to the traditional solution, which exhibits unbalanced operation, the proposed ones exploit an auxiliary high-gain feedback loop which provides differential drive, thereby highly improving the common-mode rejection ratio (CMRR). Prototypes are designed and fabricated in a 0.35-mum technology and experimental results confirm that a CMRR increase greater than 20 dB can be achieved and, for one of the two solutions, without increasing the voltage requirements.

A synthesis-oriented approach to design microwave multidevice amplifiers with a prefixed stability margin

A design methodology that allows forcing a prefixed stability margin on microwave and millimeter-wave multidevice amplifiers during the synthesis procedure performed by CAD tools is proposed. To the best of our knowledge, for the first time expressions equivalent to stability margins have been determined to guide CAD optimizers to design circuits stable under parameter variations. Stability margins discussed in this paper allow inclusion of stability requirements among yield specifications in a rigorous way. A case study of a 4-FET distributed amplifier design is presented where stability under parameter variations has been achieved by using the proposed methodology.

Switched Capacitor Sample-and-Hold Circuit with Input Signal Range beyond Supply Voltage

A switched capacitor sample-and-hold (S/H) circuit with extended dynamic range beyond the supply voltage is presented. The proposed architecture includes a gate-bootstrapped circuit and an improved flip-around S/H with two selectable configurations. Simulations in a 0.13 ¿m CMOS technology show that the new system is capable of sampling a below-ground signal and allows an interface adapter that enhances the dynamic range of the low-voltage analog-to-digital (A/D) converters without affecting the input bandwidth.

A model for the distortion due to switch on-resistance in sample-and-hold circuits

A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters

A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers

A low power monolithic Clock and Data Recovery IC for 2.5 Gb/s SDH STM-16 systems has been designed and fabricated using Maxim GST-2 27 GHz-f/sub T/ silicon bipolar technology. The circuit performs the following functions: signal amplification and limitation, clock recovery and decision; a single 3.3 V supply voltage is required, and power consumption results below 350 mW. This IC and a previously presented transimpedance amplifier so allows composing a chip set for the receiver with a total power dissipation below 0.5 W. Preliminary measurements under a 2/sup 23/-1 PRBS data stream have shown an input sensitivity below 20 mVpp and a rms jitter of 10 ps.