Marco Bucci

Three-phase dual-rail pre-charge logic

This paper investigates the design of a dual-rail pre-charge logic family whose power consumption is insensitive to unbalanced load conditions thus allowing adopting a semi-custom design flow (automatic place & route) without any constraint on the routing of the complementary wires. The proposed logic is based on a three phase operation where, in order to obtain a constant energy consumption over the operating cycle, an additional discharge phase is performed after pre-charge and evaluation. In this work, the proposed concept has been implemented as an enhancement of the SABL logic with a limited increase in circuit complexity. Implementation details and simulation results are reported which show a power consumption independent of the sequence of processed data and load capacitances. An improvement in the energy consumption balancing up to 100 times with respect to SABL has been obtained.

Design of testable random bit generators

In this paper, the evaluation of random bit generators for security applications is discussed and the concept of stateless generator is introduced. It is shown how, for the proposed class of generators, the verification of a minimum entropy limit can be performed directly on the post-processed random numbers thus not requiring a good statistic quality for the noise source itself, provided that a sufficient compression is adopted in the post-processing unit. Assuming that the noise source is stateless, a straightforward entropy estimator to drive an adaptive compression algorithm is proposed. Examples of stateless sources are also discussed. Finally, an attack scenario against a noise source is defined and an effective approach to the attack detection is presented. The entropy estimator and the attack detection together guarantee the unpredictability of the generated random numbers.

An Offset-Compensated Oscillator-Based Random Bit Source for Security Applications

In this paper, a new, patent pending, architecture for a jitter-based random bit source which is cost-effective and suitable for applications in cryptography, is presented. The source is designed to be robust against parameter variations and attacks aimed to force its output. It also features an auto-test which allows to detect faults and to estimate the source entropy. The proposed design is an enhancement of the oscillator-based architecture where a compensation loop is added to maximize the statistical quality of the output sequence, especially in presence of low-jittered oscillators. As a consequence, a fully-digital implementation, without any amplified noise source, can be adopted for the proposed generator. From an analysis of the known techniques for random number generation, the proposed architecture is derived and implementation details are also reported.

A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors

Attacks based on a differential power analysis (DPA) are a main threat when designing cryptographic processors. In this paper, a countermeasure against DPA is presented and evaluated on a case study simulation. It can be implemented, using a standard digital technology, by applying a straightforward transformation to the original design, without an actual redesign. A methodology to perform a DPA in simulation is presented which can be exploited to test the resistance of a cryptographic processor during its design flow. By using the above methodology, the proposed countermeasure shows a 30dB attenuation of the signals exploited by the DPA.

Testing power-analysis attack susceptibility in register-transfer level designs

The susceptibility of cryptographic devices to attacks based on power analysis can be both significantly and efficiently tested at early design steps. The results from a real case application show the advantages of the approach.

A Fully-Digital Chaos-Based Random Bit Generator

In this paper, the design of a fully-digital chaos-based random bit generator RBG is reported. The proposed generator exploits a chaotic system whose map is implemented in the time domain where the state variables of the system are represented by the phase of digital ring oscillators. This results in an extremely robust and efficient entropy source which can be implemented as a digital standard-cell thus overcoming the main drawbacks of chaotic RBGs. An implementation in a

Delay-based dual-rail pre-charge logic

40\,nm

INTEGRATED CIRCUIT AND METHOD FOR PREVENTING AN UNAUTHORIZED ACCESS TO A DIGITAL VALUE

CMOS technology shows a final throughput after post-processing of 12.5i¾źMbit/s at 50i¾źMHz with a worst case current consumption below