Andreas Burg

VLSI implementation of MIMO detection using the sphere decoding algorithm

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the /spl lscr//sup /spl infin//-instead of /spl lscr//sup 2/-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.

Soft-output sphere decoding: algorithms and VLSI implementation

Multiple-input multiple-output (MIMO) detection algorithms providing soft information for a subsequent channel decoder pose significant implementation challenges due to their high computational complexity. In this paper, we show how sphere decoding can be used as an efficient tool to implement soft-output MIMO detection with flexible trade-offs between computational complexity and (error rate) performance. In particular, we provide VLSI implementation results which demonstrate that single tree-search, sorted QR-decomposition, channel matrix regularization, log-likelihood ratio clipping, and imposing runtime constraints are the key ingredients for realizing soft-output MIMO detectors with near max-log performance at a chip area that is only 58% higher than that of the best-known hard-output sphere decoder VLSI implementation.

K-best MIMO detection VLSI architectures achieving up to 424 Mbps

From an error rate performance perspective, maximum likelihood (ML) detection is the preferred detection method for multiple-input multiple-output (MIMO) communication systems. However, for high transmission rates a straight forward exhaustive search implementation suffers from prohibitive complexity. The K-best algorithm provides close-to-ML bit error rate (BER) performance, while its circuit complexity is reduced compared to an exhaustive search. In this paper, a new VLSI architecture for the implementation of the K-best algorithm is presented. Instead of the mostly sequential processing that has been applied in previous VLSI implementations of the algorithm, the presented solution takes a more parallel approach. Furthermore, the application of a simplified norm is discussed. The implementation in an ASIC achieves up to 424 Mbps throughput with an area that is almost on par with current state-of-the-art implementations

MIMO transmission with residual transmit-RF impairments

Physical transceiver implementations for multiple-input multiple-output (MIMO) wireless communication systems suffer from transmit-RF (Tx-RF) impairments. In this paper, we study the effect on channel capacity and error-rate performance of residual Tx-RF impairments that defy proper compensation. In particular, we demonstrate that such residual distortions severely degrade the performance of (near-)optimum MIMO detection algorithms. To mitigate this performance loss, we propose an efficient algorithm, which is based on an i.i.d. Gaussian model for the distortion caused by these impairments. In order to validate this model, we provide measurement results based on a 4-stream Tx-RF chain implementation for MIMO orthogonal frequency-division multiplexing (OFDM).

Prototype experience for MIMO BLAST over third-generation wireless system

In this paper, a multiple-input-multiple-output (MIMO) extension for a third-generation (3G) wireless system is described. The integration of MIMO concepts within the existing UMTS standard and the associated space-time RAKE receiver are explained. An analysis is followed by a description of an actual experimental MIMO transmitter and receiver architecture, both realized on digital signal processors (DSPs) and FPGAs within a precommercial OneBTS base station. It uses four transmit and four receive antennas to achieve downlink data rates up to 1 Mb/s per user with a spreading factor of 32 and the UMTS chip rate of 3.84 MHz. Furthermore, different MIMO detectors are evaluated, comparing their performance and complexity. System performance is evaluated through simulations and indoor over-the-air measurements. Capacity and bit-error rate measurement results are presented.

VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition

The QR decomposition is an important, but often underestimated prerequisite for pseudo- or non-linear detection methods such as successive interference cancellation or sphere decoding for multiple-input multiple-output (MIMO) systems. The ability of concurrent iterative sorting during the QR decomposition introduces a moderate overall latency, but provides the base for an improved layered stream decoding. This paper describes the architecture and results of the first VLSI implementation of an iterative sorted QR decomposition preprocessor for MIMO receivers. The presented architecture performs MIMO channel preprocessing using Givens rotations in order to compute the minimum mean squared error QR decomposition

LLR-Based Successive Cancellation List Decoding of Polar Codes

We present an LLR-based implementation of the successive cancellation list (SCL) decoder. To this end, we associate each decoding path with a metric which (i) is a monotone function of the paths likelihood and (ii) can be computed efficiently from the channel LLRs. The LLR-based formulation leads to a more efficient hardware implementation of the decoder compared to the known log-likelihood based implementation. Synthesis results for an SCL decoder with block-length of N = 1024 and list sizes of L = 2 and L = 4 confirm that the LLR-based decoder has considerable area and operating frequency advantages in the orders of 50% and 30%, respectively.

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding

A Real-Time 4-Stream MIMO-OFDM Transceiver: System Design, FPGA Implementation, and Characterization

When designing complex communication systems, such as MIMO-OFDM transceivers, prototypes have become an important tool for understanding the implementation trade-offs and the system behavior. This paper presents a real-time FPGA prototype for a 4-stream MIMO-OFDM transceiver capable of transmitting 216 Mbit/s in 20 MHz bandwidth. The paper covers all parts of the system from RF to channel decoding and considers both algorithm and implementation aspects. In particular, we discuss the initial parameter estimation, channel estimation, MIMO detection, parameter tracking, and channel decoding. FPGA implementation results are reported along with measurements that demonstrate the throughput of spatial multiplexing with four spatial streams.

Computational stereo camera system with programmable control loop

Stereoscopic 3D has gained significant importance in the entertainment industry. However, production of high quality stereoscopic content is still a challenging art that requires mastering the complex interplay of human perception, 3D display properties, and artistic intent. In this paper, we present a computational stereo camera system that closes the control loop from capture and analysis to automatic adjustment of physical parameters. Intuitive interaction metaphors are developed that replace cumbersome handling of rig parameters using a touch screen interface with 3D visualization. Our system is designed to make stereoscopic 3D production as easy, intuitive, flexible, and reliable as possible. Captured signals are processed and analyzed in real-time on a stream processor. Stereoscopy and user settings define programmable control functionalities, which are executed in real-time on a control processor. Computational power and flexibility is enabled by a dedicated software and hardware architecture. We show that even traditionally difficult shots can be easily captured using our system.