Norbert Felber

K-best MIMO detection VLSI architectures achieving up to 424 Mbps

From an error rate performance perspective, maximum likelihood (ML) detection is the preferred detection method for multiple-input multiple-output (MIMO) communication systems. However, for high transmission rates a straight forward exhaustive search implementation suffers from prohibitive complexity. The K-best algorithm provides close-to-ML bit error rate (BER) performance, while its circuit complexity is reduced compared to an exhaustive search. In this paper, a new VLSI architecture for the implementation of the K-best algorithm is presented. Instead of the mostly sequential processing that has been applied in previous VLSI implementations of the algorithm, the presented solution takes a more parallel approach. Furthermore, the application of a simplified norm is discussed. The implementation in an ASIC achieves up to 424 Mbps throughput with an area that is almost on par with current state-of-the-art implementations

An Attempt to Model the Human Body as a Communication Channel

Using the human body as a transmission medium for electrical signals offers novel data communication in biomedical monitoring systems. In this paper, galvanic coupling is presented as a promising approach for wireless intra-body communication between on-body sensors. The human body is characterized as a transmission medium for electrical current by means of numerical simulations and measurements. Properties of dedicated tissue layers and geometrical body variations are investigated, and different electrodes are compared. The new intra-body communication technology has shown its feasibility in clinical trials. Excellent transmission was achieved between locations on the thorax with a typical signal-to-noise ratio (SNR) of 20 dB while the attenuation increased along the extremities.

ECC Is Ready for RFID --- A Proof in Silicon

This paper presents the silicon chip ECCon, an Elliptic Curve Cryptography processor for application in Radio-Frequency Identification. The circuit is fabricated on a 180 nm CMOS technology. ECCon features small silicon size (15K GE) and has low power consumption (8.57 μW). It computes 163-bit ECC point-multiplications in 296k cycles and has an ISO 18000-3 RFID interface. ECCons very low and nearly constant power consumption makes it the first ECC chip that can be powered passively. This major breakthrough is possible because of a radical change in hardware architecture. The ECCon datapath operates on 16-bit words, which is similar to ECC instruction-set extensions. A number of innovations on the algorithmic and on the architectural level substantially increased the efficiency of 163-bit ECC. ECCon is the first demonstration that the proof of origin via electronic signatures can be realized on RFID tags in 180 nm CMOS and below.

A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm

A VLSI implementation of the International Data Encryption Algorithm is presented. Security considerations led to novel system concepts in chip design including protection of sensitive information and on-line failure detection capabilities. BIST was instrumental for reconciling contradicting requirements of VLSI testability and cryptographic security. The VLSI chip implements data encryption and decryption in a single hardware unit. All important standardized modes of operation of block ciphers, such as ECB, CBC, CFB, OFB, and MAC, are supported. In addition, new modes are proposed and implemented to fully exploit the algorithms inherent parallelism. With a system clock frequency of 25 MHz the device permits a data conversion rate of more than 177 Mb/s. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM or FDDI. >

Electron and hole mobility in silicon at large operating temperatures. I. Bulk mobility

In this paper, an experimental investigation on high-temperature carrier mobility in bulk silicon is carried out with the aim of improving our qualitative and quantitative understanding of carrier transport under ESD events. Circular van der Pauw patterns, suitable for resistivity and Hall measurements, were designed and manufactured using both the n and p layers made available by the BCD-3 smart-power technology. The previous measurements were carried out using a special measurement setup that allows operating temperatures in excess of 400/spl deg/C to be reached within the polar expansions of a commercial magnet. A novel extraction methodology that allows for the determination of the Hall factor and drift mobility against impurity concentration and lattice temperature has been developed. Also, a compact mobility model suitable for implementation in device simulators is worked out and implemented in the DESSIS/spl copy/ code. Comparisons with the mobility models by G. Masetti et al. (1983) and D.B.M. Klaassen (1992) are shown in the temperature range between 25 and 400/spl deg/C.

Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems

A novel methodology for realizing Globally-Asynchronous Locally-Synchronous (GALS) architectures is reported. We developed a library of predesigned modules that facilitate the assembly of independently clocked modules to on-chip systems. The components of this library establish high-performance data exchange channels which are instrumental in constructing flexible architectures. The validity of our concept is proven by applying it to an ASIC design with real-world complexity.

Signal Transmission by Galvanic Coupling Through the Human Body

Galvanic coupling is a promising approach for wireless intrabody data transmission between sensors. Using the human body as a transmission medium for electrical signals becomes a novel data communication technique in biomedical monitoring systems. In this paper, special attention is given to the coupling of the current into the human body. Safety requirements have to be fulfilled, and optimal signal coupling is of essence. Therefore, different electrodes are compared. A test system offers up to 1 mA contact current modulated in the frequency range of 10 kHz to 1 MHz. The injected current is up to 20 times below the maximum allowed contact current. Such a low-current approach enables data communication that is more energy saving than other wireless technologies.

VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition

The QR decomposition is an important, but often underestimated prerequisite for pseudo- or non-linear detection methods such as successive interference cancellation or sphere decoding for multiple-input multiple-output (MIMO) systems. The ability of concurrent iterative sorting during the QR decomposition introduces a moderate overall latency, but provides the base for an improved layered stream decoding. This paper describes the architecture and results of the first VLSI implementation of an iterative sorted QR decomposition preprocessor for MIMO receivers. The presented architecture performs MIMO channel preprocessing using Givens rotations in order to compute the minimum mean squared error QR decomposition

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

The paper describes an algorithm and a corresponding VLSI architecture for the implementation of linear MMSE detection in packet-based MIMO-OFDM communication systems. The advantages of the presented receiver architecture are low latency, high-throughput, and efficient resource utilization, since the hardware required for the computation of the MMSE estimators is reused for the detection. The algorithm also supports the extraction of soft information for channel decoding

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison

The QR decomposition (QRD) is an important prerequisite for many different detection algorithms in multiple-input multiple-output (MIMO) wireless communication systems. This paper presents an optimized fixed-point VLSI implementation of the modified Gram-Schmidt (MGS) QRD algorithm that incorporates regularization and additional sorting of the MIMO channel matrix. Integrated in 0.18 mum CMOS technology, the proposed VLSI architecture processes up to 1.56 million complex-valued 4times4-dimensional matrices per second. The implementation results of this work are extensively compared to the Givens rotation (GR)-based QRD implementation of Luethi et al., ISCAS 2007. In order to ensure a fair comparison, both QRD circuits have been integrated in the same IC manufacturing technology, with equal functionality, and the same numeric precision. The comparison of the implementation results clearly showed superiority of the GR-based VLSI solution in terms of area, processing cycles, and throughput.