Wolfgang Fichtner

Low-power logic styles: CMOS versus pass-transistor logic

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

VLSI implementation of MIMO detection using the sphere decoding algorithm

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the /spl lscr//sup /spl infin//-instead of /spl lscr//sup 2/-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.

Practical design of globally-asynchronous locally-synchronous systems

In this paper we describe a complete design methodology for a globally asynchronous on-chip communication network connecting both locally-synchronous and asynchronous modules. Synchronous modules are equipped with asynchronous wrappers which adapt their interfaces to the self-timed environment and prevent metastability. These wrappers are assembled from a concise library of predesigned technology-independent elements and provide high-speed data transfer. We confirmed the validity of our concept by applying it to an ASIC design implementing the Safer crypto-algorithm.

Numerical methods for semiconductor device simulation

This paper describes the numerical techniques used to solve the coupled system of nonlinear partial differential equations which model semiconductor devices. These methods have been encoded into our device simulation package which has successfully simulated complex devices in two and three space dimensions. We focus our discussion on nonlinear operator iteration, discretization and scaling procedures, and the efficient solution of the resulting nonlinear and linear algebraic equations. Our companion paper [13] discusses physical aspects of the model equations and presents results from several actual device simulations.

Transient Simulation of Silicon Devices and Circuits

In this paper, we present an overview of the physical principles and numerical methods used to solve the coupled system of non-linear partial differential equations that model the transient behavior of silicon VLSI device structures. We also describe how the same techniques are applicable to circuit simulation. A composite linear multistep formula is introduced as the time-integration scheme. Newton-iterative methods are exploited to solve the nonlinear equations that arise at each time step. We also present a simple data structure for nonsymmetric matrices with symmetric nonzero structures that facilitates iterative or direct methods with substantial efficiency gains over other storage schemes. Several computational examples, including a CMOS latchup problem, are presented and discussed.

K-best MIMO detection VLSI architectures achieving up to 424 Mbps

From an error rate performance perspective, maximum likelihood (ML) detection is the preferred detection method for multiple-input multiple-output (MIMO) communication systems. However, for high transmission rates a straight forward exhaustive search implementation suffers from prohibitive complexity. The K-best algorithm provides close-to-ML bit error rate (BER) performance, while its circuit complexity is reduced compared to an exhaustive search. In this paper, a new VLSI architecture for the implementation of the K-best algorithm is presented. Instead of the mostly sequential processing that has been applied in previous VLSI implementations of the algorithm, the presented solution takes a more parallel approach. Furthermore, the application of a simplified norm is discussed. The implementation in an ASIC achieves up to 424 Mbps throughput with an area that is almost on par with current state-of-the-art implementations

An Attempt to Model the Human Body as a Communication Channel

Using the human body as a transmission medium for electrical signals offers novel data communication in biomedical monitoring systems. In this paper, galvanic coupling is presented as a promising approach for wireless intra-body communication between on-body sensors. The human body is characterized as a transmission medium for electrical current by means of numerical simulations and measurements. Properties of dedicated tissue layers and geometrical body variations are investigated, and different electrodes are compared. The new intra-body communication technology has shown its feasibility in clinical trials. Excellent transmission was achieved between locations on the thorax with a typical signal-to-noise ratio (SNR) of 20 dB while the attenuation increased along the extremities.

Efficient Sparse LU Factorization with Left-Right Looking Strategy on Shared Memory Multiprocessors

An efficient sparse LU factorization algorithm on popular shared memory multi-processors is presented. Pipelining parallelism is essential to achieve higher parallel efficiency and it is exploited with a left-right looking algorithm. No global barrier is used and a completely asynchronous scheduling scheme is one central point of the implementation. The algorithm has been successfully tested on SUN Enterprise, DEC AlphaServer, SGI Origin 2000 and Cray T90 and J90 parallel computers, delivering up to 2.3 GFlop/s on an eight processor DEC AlphaServer for medium-size semiconductor device simulations and structural engineering problems.

Quantum device-simulation with the density-gradient model on unstructured grids

We describe an implementation of the density-gradient device equations which is simple and works in any dimension without imposing additional requirements on the mesh compared to classical simulations. It is therefore applicable to real-world device simulation with complex geometries. We use our implementation to determine the quantum mechanical effects for a MOS-diode, a MOSFET and a double-gated SOI MOSFET. The results are compared to those obtained by a 1D-Schrodinger-Poisson solver. We also investigate a simplified variant of the density-gradient term and show that, while it can reproduce terminal characteristics, it does not give the correct density distribution inside the device.

Analysis of lateral DMOS power devices under ESD stress conditions

The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogeneous current flow due to the unusual electrical behavior are accurately analyzed in single- and multi-finger devices.