Andreas Demosthenous

An Integrated Implantable Stimulator That is Fail-Safe Without Off-Chip Blocking-Capacitors

We present a neural stimulator chip with an output stage (electrode driving circuit) that is fail-safe under single-fault conditions without the need for off-chip blocking-capacitors. To miniaturize the stimulator output stage two novel techniques are introduced. The first technique is a new current generator circuit reducing to a single step the translation of the digital input bits into the stimulus current, thus minimizing silicon area and power consumption compared to previous works. The current generator uses voltage-controlled resistors implemented by MOS transistors in the deep triode region. The second technique is a new stimulator output stage circuit with blocking-capacitor safety protection using a high-frequency current-switching (HFCS) technique. Unlike conventional stimulator output stage circuits for implantable functional electrical stimulation (FES) systems which require blocking-capacitors in the microfarad range, our proposed approach allows capacitance reduction to the picofarad range, thus the blocking-capacitors can be integrated on-chip. The prototype four-channel neural stimulator chip was fabricated in XFABs 1-mum silicon-on-insulator CMOS technology and can operate from a power supply between 5-18 V. The stimulus current is generated by active charging and passive discharging. We obtained recordings of action potentials and a strength-duration curve from the sciatic nerve of a frog with the stimulator chip which demonstrate the HFCS technique. The average power consumption for a typical 1-mA 20-Hz single-channel stimulation using a book electrode, is 200 muW from a 6 V power supply. The silicon area occupation is 0.38 mm2 per channel.

Design of a low-noise preamplifier for nerve cuff electrode recording

This paper discusses certain important issues involved in the design of a nerve signal preamplifier for implantable neuroprostheses. Since the electroneurogram signal measured from cuff electrodes is typically on the order of 1 /spl mu/V, a very low-noise interface is essential. We present the argument for the use of BiCMOS technology in this application and then describe the design and evaluation of a complete preamplifier fabricated in a 0.8-/spl mu/m double-metal double-poly process. The preamplifier has a nominal voltage gain of 100, a bandwidth of 15 kHz, and a measured equivalent input-referred noise voltage spectral density of 3.3 nV//spl radic/Hz at 1 kHz. The total input-referred rms noise voltage in a bandwidth 1 Hz-10 kHz is 290 nV, the power consumption is 1.3 mW from /spl plusmn/2.5-V power supplies, and the active area is 0.3 mm/sup 2/.

Current Conveyor-Based Square/Triangular Waveform Generators With Improved Linearity

Two second-generation current conveyor (CCII+)-based resistance-capacitance (RC) square/triangular waveform generators, which have been derived from their voltage-mode op-amp-based schemes, with independent control of frequency are presented in this paper. Each configuration consists of two positive second-generation conveyors (CCII(+)-ldquoArdquo and CCII(+)-ldquoBrdquo), three resistors, and one floating capacitor that is responsible for better linearity. The frequency of the waveform generators can independently be adjusted with any passive device. The circuits were built with commercially available current feedback operational amplifiers (AD844) and passive components used externally and tested for waveform generation and tunability. The measured results included in the paper show excellent linear variation of frequency as compared with existing reported configurations over the range from 25 Hz to 260 kHz. The configurations that are suitable for very large scale integration (VLSI) realization find application in capacitive and resistive sensors and in neuro-fuzzy systems.

Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI

Analog computations such as four-quadrant multiplication, linear voltage-to-current conversion and sum-square or difference-square are fundamental for many analog signal processing systems. All these functions can be realized based on the principle of the linearized differential pair using floating-voltage sources. This paper describes an improved practical realization of this principle, which is particularly suited to analog VLSI computational systems. The proposed class-AB analog cells are very compact, exhibit low total harmonic distortion and low nonlinearity, have a wide bandwidth, and are compatible with low-power and low-voltage operation. A mathematical discussion on stability and harmonic distortion of the proposed realization is presented. Both simulated results and measurements from fabricated cell samples in a 0.8-/spl mu/m CMOS process are given. The described circuits operate from a single 2-V power supply.

A CMOS analog winner-take-all network for large-scale applications

A CMOS scalable high-speed current-mode asynchronous winner-take-all (WTA) circuit is described. The new WTA has improved resolution and operating speed compared to other current-mode WTAs, especially for large M, where M is the number of inputs. The proposed arrangement is, therefore, well suited to applications requiring large WTA systems where operating speed and resolution are important parameters [e.g., vector quantization (VQ)]. Measurements show that the proposed circuit can resolve input currents differing by less than 1 /spl mu/A with negligible loss of operating speed. Detailed measured results and simulations are presented.

On cuff imbalance and tripolar ENG amplifier configurations

Electroneurogram (ENG) recording techniques benefit from the use of tripolar cuffs because they assist in reducing interference from sources outside the cuff. However, in practice the performance of ENG amplifier configurations, such as the quasi-tripole and the true-tripole, has been widely reported to be degraded due to the departure of the tripolar cuff from ideal behavior. This paper establishes the presence of cuff imbalance and investigates its relationship to cuff asymmetry, cuff end-effects and interference source proximity. The paper also presents a comparison of the aforementioned amplifier configurations with a new alternative, termed the adaptive-tripole, developed to automatically compensate for cuff imbalance. The output signal-to-interference ratio of the three amplifier configurations were compared in vivo for two interference signals (stimulus artifact and M-wave) superimposed on compound action potentials. The experiments showed (for the first time) that the two interference signals result in different cuff imbalance values. Nevertheless, even with two distinct cuff imbalances present, the adaptive-tripole performed better than the other two systems in 61.9% of the trials.

A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses

This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6-μ m high-voltage CMOS technology occupying an area of 2.27 mm2. The measured performance of the ASIC has been verified using vestibular electrodes in saline.

A 230-nW 10-s time constant CMOS integrator for an adaptive nerve signal amplifier

This paper describes a micropower CMOS integrator with an extremely large time constant for use in a variety of low-frequency signal processing applications. The specific use of the integrator in an implantable biomedical integrated circuit is described. The integrator is based on the OTA-C approach and a very small transconductance of 100 pA/V was achieved by cascading a short chain of transconductance-transimpedance stages. The time constant of the integrator is tunable between about 0.2 and 10 s, and any offset voltages at the output terminal can be trimmed out. The circuit was fabricated in a 0.8-/spl mu/m CMOS process, dissipates 230 nW from /spl plusmn/1.5 V power supplies (excluding the bias circuitry and output buffers) and has a core area of 0.1 mm/sup 2/. The integrator offers superior performance in terms of power consumption, die area and time constant when compared to previously published work.

A CMOS Instrumentation Amplifier With 90-dB CMRR at 2-MHz Using Capacitive Neutralization: Analysis, Design Considerations, and Implementation

The benefits of using “current feedback” in instrumentation amplifier (IA) design are well known. In this paper, we analyze the mismatch mechanisms, both random and systematic types, which influence the common-mode rejection ratio (CMRR) performance of the local current feedback IA topology. We derive analytical expressions for the common-mode gain frequency response due to random mismatches (transconductance, drain-source conductance and parasitic capacitance) and verify the integrity of the analysis through simulation. To address the systematic mismatch in the drain capacitance of the input pair transistors, we employ capacitive neutralization and verify its effectiveness in practice from the fabricated IA chip samples in a 0.35- CMOS process technology. The measured average common-mode gain improvement for the 20 fabricated samples employing our neutralization technique is about 20 dB at 2 MHz ( 3 dB bandwidth). When taking into account the differential gain response (33.7 dB), the average CMRR of the neutralized IA at 2 MHz exceeds 90 dB. The IA occupies an area of 0.068 and dissipates 0.85 mW from a 3-V power supply. The circuit is intended for a wideband bioimpedance spectroscopy application.

A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

We describe a K = 3, rate-1/2 analogue Viterbi decoder fabricated in 0.8µm CMOS technology, intended for convolutional decoding applications. The decoder is the first of its kind to employ current-mode analogue circuit techniques. It operates at data rates of at least 100Mb/s and consumes 40mW at that rate from a single 2.8V power supply. The chip contains about 6K transistors of which less than 1K are used in the analogue sections of the system and has a core area of approximately 1mm2.