Dai Jiang

A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses

This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6-μ m high-voltage CMOS technology occupying an area of 2.27 mm2. The measured performance of the ASIC has been verified using vestibular electrodes in saline.

Active Books: The Design of an Implantable Stimulator That Minimizes Cable Count Using Integrated Circuits Very Close to Electrodes

This paper presents an integrated stimulator that can be embedded in implantable electrode books for interfacing with nerve roots at the cauda equina. The Active Book overcomes the limitation of conventional nerve root stimulators which can only support a small number of stimulating electrodes due to cable count restriction through the dura. Instead, a distributed stimulation system with many tripole electrodes can be configured using several Active Books which are addressed sequentially. The stimulator was fabricated in a 0.6-μm high-voltage CMOS process and occupies a silicon area of 4.2 × 6.5 mm2. The circuit was designed to deliver up to 8 mA stimulus current to tripole electrodes from an 18 V power supply. Input pad count is limited to five (two power and three control lines) hence requiring a specific procedure for downloading stimulation commands to the chip and extracting information from it. Supported commands include adjusting the amplitude of stimulus current, varying the current ratio at the two anodes in each channel, and measuring relative humidity inside the chip package. In addition to stimulation mode, the chip supports quiescent mode, dissipating less than 100 nA current from the power supply. The performance of the stimulator chip was verified with bench tests including measurements using tripoles in saline.

An Integrated Amplifier With Passive Neutralization of Myoelectric Interference From Neural Recording Tripoles

This paper describes an integrated amplifier for neural recording from tripolar electrode books connected in the quasi-tripole arrangement. The same tripole is used in the implant for neural stimulation. To remove myoelectric interference from neural recordings, a resistor-capacitor network is used to balance the electrode impedances in the tripole. The amplifier is programmable (recording mode, passband, gain, and trimming impedance) via a serial peripheral interface. Its front-end instrumentation amplifier employs current feedback to achieve high common-mode rejection ratio. The circuit was implemented in 0.35- μm CMOS technology and occupies an area of ~1.2 mm2. In the very-low noise mode, the analog front-end features a maximum of 0.68 μVrms input-referred noise in the passband and consumes ~310 μA from a 3 V supply. The measured common-mode rejection ratio of the instrumentation amplifier (CMRRIA) approaches 100 dB. The effect of component mismatch on the CMRRIA and the noise performance of the instrumentation amplifier are examined. In addition, the recording tripole is analyzed to derive the overall common-mode rejection ratio that is shown to exceed 80 dB. The ability of the neural amplifier to reduce myoelectric interference is demonstrated. The amplifier is also tested with a tripole immersed in saline in the stimulate-record mode.

A fast passive phase shift keying modulator for inductively coupled implanted medical devices

This paper presents an integrated modulator for inductively coupled biomedical telemetry. The circuit implements passive phase shift keying (PPSK) modulation and is designed to work at 13.56 MHz with a single pair of coils for both data transmission and power delivery. The data link can reach data rates up to 1/16 of the carrier frequency, i.e., 847.5 kbps in this case. To our knowledge, it is the fastest data rate achieved by a single wireless link used simultaneously for power delivery and communication in implanted medical devices. The circuit was fabricated in a 0.6-μm CMOS technology, occupies a silicon area of 0.7 mm2 and dissipates about 2 mW from a 5 V power supply at full speed of operation.

A Vestibular Prosthesis With Highly-Isolated Parallel Multichannel Stimulation

This paper presents an implantable vestibular stimulation system capable of providing high flexibility independent parallel stimulation to the semicircular canals in the inner ear for restoring three-dimensional sensation of head movements. To minimize channel interaction during parallel stimulation, the system is implemented with a power isolation method for crosstalk reduction. Experimental results demonstrate that, with this method, electrodes for different stimulation channels located in close proximity ( mm) can deliver current pulses simultaneously with minimum inter-channel crosstalk. The design features a memory-based scheme that manages stimulation to the three canals in parallel. A vestibular evoked potential (VEP) recording unit is included for closed-loop adaptive stimulation control. The main components of the prototype vestibular prosthesis are three ASICs, all implemented in a 0.6- μm high-voltage CMOS technology. The measured performance was verified using vestibular electrodes in vitro.

A New Mechanism Producing Discrete Spurious Components in Fractional-

Fractional- frequency synthesizers have long been known to suffer from a set of spurious components, often referred to as fractional spurs, which are usually attributed to the operation of the modulator. This paper proposes a new phenomenon-based on cross-coupling and sampling of the nonharmonically related signals present in such synthesizers-which is capable of producing a family of spurious components of identical form to fractional spurs, with support from a range of analytic, simulated and measured results. A unique experimental arrangement is described, allowing controlled cross-coupling of signals within a synthesizer, which provides convincing experimental validation of this mechanism. Finally, techniques are suggested to allow at least partial mitigation of the effect.

N

An integrated amplifier for electroneurogram (ENG) recordings from tripolar cuff electrodes is described. The amplifier is dedicated to urinary incontinence and other functional electrical stimulation (FES) applications. To remove myoelectric (EMG) interference a parallel RC network is used to balance the electrode impedances in the quasi-tripole amplifier configuration. The various ENG amplifier settings, such as resistance and capacitance trimming for the neutralization RC network, amplifier gain and filter cut-off frequencies, are controlled by an external microcontroller which communicates with the embedded SPI (Serial Port Interface) block in the amplifier. By this topology control of the ENG amplifier is executed in software allowing for the system parameters to be re-configured after implantation. The analog system blocks and details of the SPI logic are described. The amplifier was fabricated in a 3-V 0.35-mum BiCMOS process technology and preliminary measured results are reported. Input signals as low as 1muV can be reliably detected. The amplifier occupies an area of 1.5mm2 and consumes about 1.4mW when configured to detect sub-microvolt neural signals.

Frequency Synthesizers

This paper describes the stimulation management unit for a multichannel vestibular neural prosthesis. The unit is designed as part of a stimulator ASIC in the implantable subsystem of the prosthesis. This digital unit provides the stimulator ASIC the ability to generate biphasic current pulses at specified amplitude, duration and pulse rate to drive electrodes in the semicircular canals. The circuit was implemented in 0.6-μm CMOS technology and post-layout simulations are presented to show its operation.

A programmable ENG amplifier with passive EMG neutralization for FES applications

This paper describes the design of a new technique and architecture of multi-modulus divider for Sigma-Delta fractional-N PLL frequency synthesisers. The proposed architecture uses a memory-controlled technique that can achieve a wider range of prescaler modulus values, more flexible operation, and lower power dissipation. It has been implemented in an FPGA in conjunction the store-sequence architecture and a range of Sigma-Delta modulators. Both simulated and measured results are shown to demonstrate that a substantial improvement in performance is possible.

Stimulation management for a multichannel vestibular neural prosthesis

This paper studies the stable boundary of a type of third-order one-bit sigma-delta modulator (/spl Sigma//spl Delta/M) using an extended describing function method in which both the amplitude and phase shift of a sampled quantiser are modelled. By determination of the maximum DC input for the feedback coefficients of the sigma-delta modulator, the performance of the system can be optimised for stable modulator operation. This approach is potentially useful in the design and stability analysis of higher-order /spl Sigma//spl Delta/Ms.