Andreas Herkersdorf

Technologies and building blocks for fast packet forwarding

We provide a review of the state of the art and the future of packet processing and switching. The industrys response to the need for wire-speed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special programmable network processors. We discuss the prerequisites of processing tens to hundreds of millions of packets per second and indicate ways to achieve scalability through parallel packet processing. Tomorrows switch fabrics, which will provide node-internal connectivity between the input and output ports of a router or switch, will have to sustain terabit-per-second throughput. After reviewing fundamental switching concepts, we discuss architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance.

Early analysis tools for system-on-a-chip design

The paper describes the need for early analysis tools to enable developers of todays system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.

A scalable SDH/SONET framer architecture for datacom and telco applications

This paper presents the architectural concepts behind a versatile VLSI device that maps ATM, IP, and/or traditional T1/T3 traffic streams into SONET/SDH transport signals ranging from OC-1 to OC-48/STM-16. Additional key features for effective system integration are on-chip support for add-drop multiplexing, digital cross-connect, and automatic protection switching functions. A roadmap discussing the applicability of the developed concepts for next-generation framers up to OC-192/STM-64 is also presented.

Design methodology for a large communication chip

The example chip operates with 14 externally provided system clocks plus four clocks recovered from input data streams and 36 corresponding internal clock domains, it also couples a large digital design to a mixed-signal part in physical design.

A scalable modular architecture for SDH/SONET technology

A scalable architecture for integrated SDH/SONET framers is presented. It exploits the fact that not only those framer functions that are obviously suited for parallel processing but all SDH/SONET overhead processing and most of the payload processing functions can be implemented as distributed algorithms. Thereby an M/spl times/STM-N framer also handles STM-M/spl times/N and STM-(M/spl times/N)c frames. These distributed algorithms cover frame scrambling, overhead byte processing, ATM and PPP payload handling, and interface implementations. A series of modular building blocks for this architecture and first complete framers is now available.

Route discovery for multistage fabrics in ATM switching nodes

This paper presents an intra-node Route Discovery Protocol (RDP) applicable to multistage switch fabrics in nodes of ATM Local Area Networks (LANs), as well as in transit nodes of future high-speed Metropolitan or Wide Area Networks (MANs or WANs). The proposed RDP automatically builds and periodically updates routing tables in each network adapter. These routing tables contain the mapping between the logical adapter addresses and the currently available physical routes through the multistage switch fabric to all other adapters attached to the node. In addition, functional entities located at specific adapters are detected and associated with physical routes in the routing tables. Detecting all routes during system startup is the basis for fast connection setup with low latency. By periodically monitoring all possible table entries, our protocol provides continuous supervision of the nodes internal link status and can support possible higher-layer extensions to perform load balancing over alternative routes. Small control buffers in network adapters, which are typical for practical implementations, may lead to overflow conditions and, thus, to incompletely updated routing tables. An effective stochastic solution to this problem is presented and it will be shown through probabilistic analysis that reasonably small buffer sizes suffice for executing RDP with sufficient robustness.