Andreas Tockhorn

Rapid Evolution of Time-Efficient Packet Classifiers

Communication networks today are facing an ever increasing network traffic as well as raising quality-of-service agreements, which together demand for high performance network routers. Since a router has to search a large set or routing rules for every incoming packet, it normally utilizes efficient search mechanisms, such as trees or hash tables. This paper evolves hash functions directly in hardware and also discusses an improved initialization process. On a benchmark test consisting of 65,536 routing rules, the final hash functions consume an average of about 1.3 memory accesses for rule searching for every incoming data packet.

Modeling temperature distribution in Networks-on-Chip using RC-circuits

As transistor dimensions are shrinking into regions of only a few atomic layers, designers are faced with various problems including increased reliability and power issues. Since these problems are amplified by higher circuit temperatures, this paper proposes an approach for the fine-grained modeling of temperature distribution in many-core systems based on Networks-on-Chip. With this model, algorithms can be developed that consider the significant impact of temperature ─ e.g. on performance, power or reliability. To simulate the dynamic nature of temperature, the thermal properties of according integrated systems are modeled through the instantiation of equivalent RC-circuits. This approach exploits the dualism between electrical and thermal flows of energy. Finally, an application with system control for task mapping and power management exemplifies the proposed simulation methodology.

Simulation of thermal behavior for Networks-on-Chip

Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced. VulcaNoCs is designed to enable simultaneous execution of both high-level system simulation and dynamic modeling of temperature distributions in NoC-based systems. To emulate a systems thermal properties equivalent RC-circuits are used, exploiting the dualism between heat flow and electrical phenomena. To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5% for modeling a 2×2 NoC, for example.

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown

Because of the aggressive scaling into the nanometer regime, degradation due to wearout significantly impairs design parameters. For instance, such wearout is caused by gate oxide breakdown, which decreases the operating lifetime of integrated circuits to an extent that cannot be neglected by circuit designers to date. In this paper, we introduce an approach which applies selective redundancy to different combinational designs in order to improve reliability as regards gate oxide breakdown. Therefore, the most vulnerable transistor stacks of standard cells are doubled based on activity and the propagation delay of the design. Finally, reliability improvements of up to 75% are presented that are gained with Spice simulations. Such improvements come at the price of overhead for area and power consumption as well as delay of at most 14%. However, it is interesting to notice that the initial delay penalty of our enhanced designs finally turn into a timing advantage, as the designs are more and more affected by wearout over time. Hence, this advantage translates into further reliability improvements when clock requirements are also considered. Besides, it needs to be noted that the presented strategies can additionally improve defect yield.

Utilizing parallelism of TMR to enhance power efficiency of reliable ASIC designs

Due to aggressive scaling, reliability issues influence the design process of integrated circuits more and more. A well known technique to tackle these issues represents Triple Modular Redundancy (TMR). It strongly improves reliability of a design at the expense of at least tripled area and power consumption. In this contribution, we propose an enhanced TMR approach that significantly decreases the power overhead of conventional TMR designs. Therefore, the control logic was modified so as to switch between a TMR mode and a parallel mode. This parallel mode allows the circuit to operate with decreased frequency without losing performance by taking advantage of the parallelism offered by the tripled design. Achieved results of investigations on the ISCAS benchmark circuits show power savings of up to 50 % with a small reliability penalty compared to a conventional TMR approach for permanent failures. We also propose strategies how to utilize both operating modes in order to balance the design concerning reliability and power consumption requirements at runtime.

Accelerating the Evolution of Evolvable Hardware-based Packet Classifiers

In modern networks, the requirements towards network equipment rise together with the bandwidth. Customers and Internet service providers ask for more and more services like Voice-over-IP, IP-TV, and data services with a dependable quality. To satisfy these demands, the requirements towards packet classification as key functionality in network equipment, e.g., routers become overwhelming. We developed a packet classifier based on an evolvable hardware hash function and investigated its performance with real world data. The performance did show a reasonable degradation compared to random numbers. The computation time, which is required for evolving one generation in the genetic algorithm, corresponds to the actual fitness. We did find possibilities to maximize the speed of fitness evaluation by taking advantage of the fact, that the whole packet classifier including the fitness evaluation module is a pure hardware implementation based on FPGA technology. We were thus able to increase the performance of the evolvable packet classifier significantly while limiting the additional required hardware resources

Monitoring and Control of Temperature in Networks-on-Chip

Increasing integration densities and the emergence of nanotechnology cause issues related to reliability and power consumption to become dominant factors for the design of modern multi-core systems. Since the arising problems are enforced by high circuit temperatures, monitoring and control of on-chip temperature profiles need to be considered during design phase as well as during system operation. Hence, in this paper different approaches for the realization and integration of a monitoring system for temperature in multi-core systems based on Networks-on-Chip (NoCs) in combination with Dynamic Frequency Scaling (DFS) are investigated. Results show that both combinations using event-driven and time-driven forwarding more than double overall execution time and considerably reduce throughput of application data. Regarding performance of notification and reaction to temperature development event-driven forwarding clearly outperforms time-driven forwarding.

Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown

Because of the aggressive scaling of integrated circuits and the given limits of atomic scales, circuit designers have to become more and more aware of the arising reliability and yield concerns. So far, only very little research efforts have been put into low-level approaches for lifetime reliability, whereas lots of efforts have focused on soft-errors and system-level solutions. In this paper, we introduce and compare three diverse design approaches which apply redundancy on different abstraction levels to enhance the reliability of a Wallace multiplier as regards gate oxide breakdown. The results of the test design were further improved by adding transistors and gates with different gate oxide thicknesses. The achieved results show that lifetime reliability increases up to 200 % at constant delay by adding redundant gates, subsequently called Twin Logic Gates. However, this comes at the price of overhead for area as well as power consumption. Furthermore, it needs to be noted that the presented strategies can additionally improve defect yield.

Automated Insertion of Twin Gates to improve Reliability concerning Gate Oxide Breakdown

Scaling device dimensions towards atomic scales leads to increased reliability and yield concerns which considerably affects the work of integrated circuit designers. Furthermore, the complexity of integrated systems increases which leads to a demand for tool assisted reliability insertion during the design process. Lots of research efforts have focused on softerrors and system-level approaches. However, only few low-level solutions have been published to enhance lifetime reliability. Investigations in this field have reached an up to 200 % increased reliability concerning gate oxide breakdown if so called Twin Gates have been inserted. This contribution comprehensively presents algorithms to implement these redundant cells automatically during logic synthesis. Besides the placement in the whole design process, approaches are provided to insert Twin Gates correctly considering timing and area issues.