Claas Cornelius

Dynamic Circuit Techniques in Deep Submicron Technologies: Domino Logic reconsidered

Dynamic circuit techniques offer potential advantages over static CMOS. Domino circuits are the most widespread representative in high performance designs but suffer increasingly from deep submicron effects. This paper presents evaluations in terms of area, power dissipation, and propagation delay for static CMOS as well as for several Domino derivatives in a 90 nm technology. Finally, issues of reliability gained from practical experience for different testbenches are discussed

Modeling temperature distribution in Networks-on-Chip using RC-circuits

As transistor dimensions are shrinking into regions of only a few atomic layers, designers are faced with various problems including increased reliability and power issues. Since these problems are amplified by higher circuit temperatures, this paper proposes an approach for the fine-grained modeling of temperature distribution in many-core systems based on Networks-on-Chip. With this model, algorithms can be developed that consider the significant impact of temperature ─ e.g. on performance, power or reliability. To simulate the dynamic nature of temperature, the thermal properties of according integrated systems are modeled through the instantiation of equivalent RC-circuits. This approach exploits the dualism between electrical and thermal flows of energy. Finally, an application with system control for task mapping and power management exemplifies the proposed simulation methodology.

Simulation of thermal behavior for Networks-on-Chip

Due to increasing integration densities and the emergence of nanotechnology, especially reliability and power related design aspects become critical for chip design. Since the arising problems are enforced by high circuit temperatures, the need for a possibility to model thermal behavior of a system in an accurate and physically correct way becomes inevitable. Hence, in this paper VulcaNoCs, a SystemC-based simulation environment for systems based on NoCs, is introduced. VulcaNoCs is designed to enable simultaneous execution of both high-level system simulation and dynamic modeling of temperature distributions in NoC-based systems. To emulate a systems thermal properties equivalent RC-circuits are used, exploiting the dualism between heat flow and electrical phenomena. To verify the temperature model, VulcaNoCs is compared to a more commonly used SPICE-based approach, exhibiting significant increases in simulation performance of up to 98,5% for modeling a 2×2 NoC, for example.

Encountering gate oxide breakdown with shadow transistors to increase reliability

Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Tradition-ally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards op-erational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does im-prove system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an al-gorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transis-tors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark cir-cuits and prove the combined approach successful. The enhanced designs were on average 41.8% more reliable compared to the ini-tial designs in respect of TDDB at the price of moderately in-creased power consumption and delay.

Mapping a Pipelined Data Path onto a Network-on-Chip

During the last years, networks-on-chip (NoCs) have become a true alternative for the design of complex integrated systems-on-chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and quality-of-service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design paradigms actually tip the scales for the chosen application domain. In this paper, we discuss the level of QoS needed in a specific NoC for a packet processing application. This is done in the light of preliminary investigations for the redesign of an existing packet processing system because that systems current architecture exhibits drawbacks regarding performance and further scalability. Therefore, we considered to take advantage of an NoC communication architecture. A simple NoC was developed, which knowingly omits sophisticated QoS mechanisms. Relying on the lessons, which have learned from the history and development of the Internet, we argue that a simple and plain NoC suffices for applications as the one discussed.

Functional enhancements of TMR for power efficient and error resilient ASIC designs

Progressive technology scaling raises the need for efficient VLSI design methods facing the increasing vulnerability to permanent physical defects, while considering power efficiency of resulting circuit implementations at the same time. Triple Modular Redundancy (TMR) represents a common method to encounter reliability problems, but has the drawback of increased area and power consumption. This work introduces a Low Power Redundant (LPR) design solution that targets the power penalty of TMR implementations. This is done by enhanced and new functional runtime capabilities for error detection and operation control. By exploiting the inherent modularity and parallelism of TMR, the LPR solution applies additional control logic to switch dynamically between compare phases (to indicate faults and their locations) and parallel operation (with reduced operation frequency). This allows power optimized circuit operation with full support for the treatment of permanent faults. Simulation results on different ALU implementations show a decrease of power consumption of up to 60 % compared to conventional TMR. Furthermore, different strategies for the switching between operation modes are introduced that enable power efficient system operation in the presence of permanent physical defects. Moreover, significant reliability improvements are also achieved due to the adaptive use of the redundant modules.

Deep Submicron Technology: Opportunity or Dead End for Dynamic Circuit Techniques

Dynamic circuit techniques offer potential advantages over static CMOS, especially if more complex logic is to be implemented. Therefore, they are extensively used in high performance designs to speed up critical subsystems. However, the speed benefit is traded off for increased power consumption, area overhead, design effort, and reduced noise margins. The continuing process of technology scaling raises further concerns of reliability and limits the wide use of dynamic logic. This paper presents evaluations in terms of area, power dissipation, and propagation delay for several dynamic logic styles as well as for static CMOS in a 90 nm technology. The intention is to assess if dynamic circuit techniques are still an option to boost performance against the background of the issues of nanotechnology. Moreover, issues of reliability and signal integrity, gained from practical experience for different testbenches, and possible solutions are discussed. Finally, an automated design flow for dynamic logic, derived from a standard CMOS flow, is presented

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown

Because of the aggressive scaling into the nanometer regime, degradation due to wearout significantly impairs design parameters. For instance, such wearout is caused by gate oxide breakdown, which decreases the operating lifetime of integrated circuits to an extent that cannot be neglected by circuit designers to date. In this paper, we introduce an approach which applies selective redundancy to different combinational designs in order to improve reliability as regards gate oxide breakdown. Therefore, the most vulnerable transistor stacks of standard cells are doubled based on activity and the propagation delay of the design. Finally, reliability improvements of up to 75% are presented that are gained with Spice simulations. Such improvements come at the price of overhead for area and power consumption as well as delay of at most 14%. However, it is interesting to notice that the initial delay penalty of our enhanced designs finally turn into a timing advantage, as the designs are more and more affected by wearout over time. Hence, this advantage translates into further reliability improvements when clock requirements are also considered. Besides, it needs to be noted that the presented strategies can additionally improve defect yield.

Reliability enhancement via Sleep Transistors

CMOS is still the predominating technology for digital designs with no identifiable concurrence in the near future. Driving forces of this leadership are the high miniaturization capability and the reliability of CMOS. The latter, though, is decreasing with an alarming pace against the background of technologies with sizes at the nanoscale. The consequence is a rising demand of solutions to improve lifetime reliability and yield of todays integrated systems. Thereby, a common solution is the redundant implementation of components. However, redundancy collides with another major issue of integrated circuits — power dissipation. The main contribution of this work is an approach that increases the lifetime reliability at only low delay and power penalty. Therefore, the well-known standby-leakage reduction technique “Sleep Transistors” is combined with the idea of redundancy. Additional, we propose an extended flow for reliability verification on transistor level. Simulation results indicate that the new approach can increase the lifetime reliability by more than factor 2 compared to initial designs.

Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits

CMOS is furthermore the most widespread technology for digital designs as no feasible alternative is in sight to date and in the near future. The fundamental causes for this supremacy so far are the capability for miniaturization as well as the reliability and robustness of CMOS. Against the background of nanotechnology though, reliability concerns are arising with an alarming pace. The consequence is an increasing demand for approaches to improve both yield and lifetime reliability of today’s complex integrated systems. Hence, a common solution is the redundant implementation of components. However, redundancy contradicts those other efforts in order to cope with power dissipation. Thus, the essential contribution of this work is an approach that increases the lifetime reliability of integrated circuits while delay and power penalties are kept to a minimum. Accordingly, “Sleep Transistors” (as a common technique to reduce standby leakage) are combined with the idea of modular redundancy. Furthermore, we propose an extended flow for the quantification of reliability on transistor level. Finally, the presented simulation results evidence that the suggested approach increases the lifetime reliability by more than a factor of two compared to initial designs.