Andreas Weichslgartner

DAARM: design-time application analysis and run-time mapping for predictable execution in many-core systems

Future many-core systems are envisaged to support the concurrent execution of varying mixes of different applications. Because of the vast number of binding options for such mixes on heterogeneous resources, enabling predictable application execution is far from trivial. Hybrid application mapping is an efficient way of achieving run-time predictability by combining design-time analysis of application mappings with run-time management. Existing hybrid mapping strategies focus on computation resources and either ignore communication details or make significantly simplifying assumptions like unlimited bandwidth or exclusive usage. But, actual many-core systems consist of constrained and shared computation and communication resources where the run-time decision of whether a feasible application binding on a set of preoccupied resources exists or not is an NP-complete problem. As a remedy, we present a novel hybrid application mapping approach that considers constrained shared communication and computation resources. Here, (a) a design space exploration coupled with a formal performance analysis delivers several resource reservation configurations with verified real-time guarantees for each individual application. The configurations are then transformed to (b) a novel efficient intermediate representation that is passed to the run-time management where we (c) formulate run-time resource reservation and application binding as a constraint satisfaction problem and present an adequate solving mechanism. Our experimental evaluation shows that existing approaches may produce infeasible outcomes and are thus not applicable for predictable application execution, while the proposed approach enables predictable and efficient run-time management of dynamic application mixes.

Dynamic decentralized mapping of tree-structured applications on NoC architectures

This paper presents a novel application-driven and resource-aware mapping methodology for tree-structured streaming applications onto NoCs. This includes strategies for mapping the source of streaming applications (seed point selection), as well as embedding strategies so that each process autonomously embeds its own succeeding tasks. The proposed embedding strategies only consider the local view of neighboring cells on the NoC which allows to significantly reduce computation and monitoring overhead. Our vision is that this approach facilitates self-organizing embedded systems that provide the flexibility and fault-tolerance required in future silicon technologies. The results provided in this paper show that our local and decentralized algorithms can compete with previously presented global and centralized algorithms.

Virtual networks -- distributed communication resource management

Networks-on-Chip (NoC) enable scalability for future manycore architectures, facilitating parallel communication between multiple cores. Applications running in parallel on a NoC-based architecture can affect each other due to overlapping communication. Quality-of-Service (QoS) must be supported by the communication infrastructure to execute communication-, real-time- and safety-critical applications on such an architecture. Different strategies have been proposed to provide QoS for point-to-point connections. These strategies allow each node to set up a limited number of connections to other nodes. In this work Virtual Networks (VN) are proposed to enable QoS for regions of a NoC-based architecture. Virtual Networks overcome the limitation of point-to-point connections. A VN behaves like an exclusive physical network. Virtual Networks can be defined and configured during runtime. The size of the VN region and the assigned bandwidth can be adjusted depending on the application requirements. Virtual Networks enable the decoupling of local from global communication. Therefore, the communication of the application mapped into the region is assigned to a Virtual Network established in that specific region. This concept targets packet-switched networks with virtual channels and is realized by an intelligent hardware unit that manages the virtual channel reservation process at system runtime. Virtual Networks can be established and administrated independent of each other, enabling distributed communication resource management. The proposed concept is implemented as a cycle-accurate SystemC simulation model. The simulation results of executing communicating graphs obtained from real application highlight the usefulness of Virtual Networks by showing improved throughput and reduced delay in the respective scenarios. A hardware implementation demonstrates a low impact on area utilization and power consumption.

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, concurrent applications with different QoS requirements affect each other through overlapping communication. Therefore computation resources may not be efficiently utilized because the required communication resources are already occupied. Hence, an efficient resource management strategy is required that ensures fair sharing of communication resources between applications. Decentralized strategies provide better scalability in many-core systems. In this paper, we propose a hardware supported decentralized NoC resource management strategy. Our concept enables to define NoC regions through decentralized reconfigurable resource management policies. It offers improved performance and communication resource allocation within the regions. The proposed concept is investigated through simulation of real world application scenarios. The simulation results highlight the performance benefit within the region and the increased probability for successful reservation of communication resources. Implementation results show the low area overhead of the proposed hardware support.

Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs

Different applications concurrently running on modern MPSoCs can interfere with each other when they use shared resources. This interference can cause side channels, i.e., sources of unintended information flow between applications. To prevent such side channels, we propose a hybrid mapping methodology that attempts to ensure spatial isolation, i.e., a mutually-exclusive allocation of resources to applications in the MPSoC. At design time and as a first step, we compute compact and connected application mappings (called shapes). In a second step, run-time management uses this information to map multiple spatially segregated shapes to the architecture. We present and evaluate a (fast) heuristic and an (exact) SAT-based mapper, demonstrating the viability of the approach.

CAP: Communication Aware Programming

Networks on Chip (NoC) come along with increased complexity from the implementation and management perspective. This leads to higher energy consumption and programming complexity of NoC architectures. This work introduces communication aware programming to address communication resource management and efficient programming of NoC architectures. A programming interface is introduced to express communication requirements at the language level. These requirements are evaluated by an operating system component, which configures the communication hardware accordingly. The proposed concept enables an intuitive use of NoC features like end-to-end connections and Direct Memory Access (DMA). The presented results show that communication aware programming can improve performance and energy consumption.

Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing

The predictability of execution qualities including timeliness, power consumption, and fault-tolerability is of utmost importance for the successful introduction of multi-core architectures in embedded systems requiring guarantees rather than best effort behavior. Examples are real-time and/or safety-critical parallel applications. In particular for future many-core architectures, analysis tools for proving such properties to hold for a given application irrespective of other workload either suffer from computational complexity. Or, sound bounds are of no practical interest due to severe interferences of resources and software at multiple levels. In view of abundant computational and memory resources becoming available, we propose to apply the principles of invasive computing to avoid sharing of resources at run time as much as possible. We subsequently show that statically proven quality guarantees may be enforced on many multi-core architectures by a presented hybrid mapping approach. Rather than fixed resource mappings, this approach provides only constellations of resource allocations to the run-time system that searches for such constellations and assigns the invader a suitable claim of resources, if possible. We have implemented this hybrid approach and the interface to the language InvadeX10, a library-based extension of the X10 programming language. In this extension, so-called requirements on execution qualities such as deadlines (e.g., in the form of latency constraints) may be annotated to individual programs or even program segments. These are then translated into satisfying resource constellations that need to be found at run time prior to admitting a parallel application to start, respectively continue in view of required execution quality requirements. We give a real-world case study from the domain of heterogeneous robot vision to demonstrate the capabilities of this approach to guarantee statically analyzed best and worst-case timing requirements on latency and throughput.

Fault-tolerant communication in invasive networks on chip

Dependability and fault tolerance will play an ever increasing role when using future technology nodes. The paper presents a fault-tolerance strategy for invasive networks on chip (i-NoC). The strategy focuses on permanent faults, resulting from either process fluctuations or aging effects and briefly outlines counter measurements against transient faults. We propose a scalable scheme for detection and localization of defects in NoCs. The localization scheme is used as a basis for disabling faulty routers. We propose a transparent bypass scheme to circumvent faulty routers and regions. It uses an architecture extension in the form of an additional lightweight network layer. The fault tolerance layer can be configured at run time according to the current fault map of the architecture. The presented evaluations analyze the fault coverage of the proposed detection and localization strategy. We also investigate the implementation cost and performance impact of the fault tolerance network layer.

Providing security on demand using invasive computing

Abstract The invasive computing paradigm offers applications the possibility to dynamically spread their computation in a multicore/multiprocessor system in a resource-aware way. If applications are assumed to act maliciously, many security problems arise. In this acticle, we discuss different ways to deal with security problems in a resource-aware way. We first formalize the attacker model and the different security requirements that applications may have in multi-core systems. We then survey different hardware and software security mechanisms that can be dynamically configured to guarantee security on demand for invasive applications.

Invasive computing for timing-predictable stream processing on MPSoCs

Abstract Multi-Processor Systems-on-a-Chip (MPSoCs) provide sufficient computing power for many applications in scientific as well as embedded applications. Unfortunately, when real-time requirements need to be guaranteed, applications suffer from the interference with other applications, uncertainty of dynamic workload and state of the hardware. Composable application/architecture design and timing analysis is therefore a must for guaranteeing real-time applications to satisfy their timing requirements independent from dynamic workload. Here, Invasive Computing is used as the key enabler for compositional timing analysis on MPSoCs, as it provides the required isolation of resources allocated to each application. On the basis of this paradigm, this work proposes a hybrid application mapping methodology that combines design-time analysis of application mappings with run-time management. Design space exploration delivers several resource reservation configurations with verified real-time guarantees for individual applications. These timing properties can then be guaranteed at run-time, as long as dynamic resource allocations comply with the offline analyzed resource configurations. This article describes our methodology and presents programming, optimization, analysis, and hardware techniques for enforcing timing predictability. A case study illustrates the timing-predictable management of real-time computer vision applications in dynamic robot system scenarios.