Ralf König

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

In many-core architectures different distributed applications are executed in parallel. The applications may need hard guarantees for communication with respect to latency and throughput to cope with their constraints. Networks on Chip (NoC) are the most promising approach to handle these requirements in architectures with a large number of cores. Dynamic reservation of communication resources in virtual channel NoCs is used to enable quality of service for concurrent communication. This paper presents a router design supporting best effort and connection-oriented guaranteed service communication. The communication resources are shared dynamically between the two communication schemes. The key contribution is a concept for virtual channel reservation supporting different bandwidth and latency guarantees for simultaneous guaranteed service communication flows. Different to state-of-the-art, the used scheduling approach allows to give hard guarantees regarding throughput and latency. The concept enables to adjust the bandwidth and latency requirements of connections at run-time to cope with dynamically changing application requirements. Due to its distributed reservation process and resource allocation it offers good scalability for many-core architectures. The implementation of a router and the required extension of a network interface to support the proposed concept are presented. The software perspective is discussed. An algorithm is presented that is used to establish guaranteed service connections according to the applications bandwidth requirements. Simulation results are compared to state-of-the-art arbitration schemes and show significant improvements of latency and throughput, e.g. for an MPEG4 application. Synthesis results expose the low area overhead and impact on energy consumption which makes the concepts highly attractive for QoS-constraint many-core architectures.

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling

Networks on Chip are the most promising approach to cope with communication requirements in future many core SoCs. Depending on the executed applications, communication requirements may vary at run-time. Dynamic reservation of communication resources in virtual channel NoCs is an encouraging approach for connection-oriented communication guaranteeing QoS. This paper presents a concept enhancing virtual channel reservation to support different bandwidth and latency guarantees. The used weighted round robin scheduling provides hard guarantees regarding throughput and latency. The proposed router design enables dynamic sharing of communication resources between connectionless Best Effort and connection-oriented Guaranteed Service traffic. Due to decentralized routing and resource management it offers a very good scalability for future many core architectures. Simulation results are obtained from a 10x10 NoC with a cycle accurate SystemC router model. The presented results are compared to existing round robin arbitration schemes and show the advantage of the proposed concept. Synthesis results expose its low area overhead.

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip

This paper describes the RTL-to-layout implementation of the PACT XPP-III coarse-grained reconfigurable architecture (CGRA). The implementation activity was strictly based on a hierarchical approach in order to exploit performance optimization at all levels, as well as guarantee maximum scalability and provide a portfolio of IP-blocks that could be reused to build different configurations and embodiments of the same CGRA template. The final result can be seamlessly introduced in any SoC design flow as embedded accelerator. It is designed in STMicroelectronics 90nm GP technology, occupies 42.5 mm2, delivers 13 16-bit GOPS (0.8 GOPS/mW, 10 MOPS/mW) and has a measured max frequency of 150 MHZ, requiring a measured 13 mW/MHz dynamic power, 93 mW static. A silicon prototype was also produced embedding XPP-III in a complex system-on-chip including an ARM processor as system controller as well as different ASIC blocks.

Virtual networks -- distributed communication resource management

Networks-on-Chip (NoC) enable scalability for future manycore architectures, facilitating parallel communication between multiple cores. Applications running in parallel on a NoC-based architecture can affect each other due to overlapping communication. Quality-of-Service (QoS) must be supported by the communication infrastructure to execute communication-, real-time- and safety-critical applications on such an architecture. Different strategies have been proposed to provide QoS for point-to-point connections. These strategies allow each node to set up a limited number of connections to other nodes. In this work Virtual Networks (VN) are proposed to enable QoS for regions of a NoC-based architecture. Virtual Networks overcome the limitation of point-to-point connections. A VN behaves like an exclusive physical network. Virtual Networks can be defined and configured during runtime. The size of the VN region and the assigned bandwidth can be adjusted depending on the application requirements. Virtual Networks enable the decoupling of local from global communication. Therefore, the communication of the application mapped into the region is assigned to a Virtual Network established in that specific region. This concept targets packet-switched networks with virtual channels and is realized by an intelligent hardware unit that manages the virtual channel reservation process at system runtime. Virtual Networks can be established and administrated independent of each other, enabling distributed communication resource management. The proposed concept is implemented as a cycle-accurate SystemC simulation model. The simulation results of executing communicating graphs obtained from real application highlight the usefulness of Virtual Networks by showing improved throughput and reduced delay in the respective scenarios. A hardware implementation demonstrates a low impact on area utilization and power consumption.

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, concurrent applications with different QoS requirements affect each other through overlapping communication. Therefore computation resources may not be efficiently utilized because the required communication resources are already occupied. Hence, an efficient resource management strategy is required that ensures fair sharing of communication resources between applications. Decentralized strategies provide better scalability in many-core systems. In this paper, we propose a hardware supported decentralized NoC resource management strategy. Our concept enables to define NoC regions through decentralized reconfigurable resource management policies. It offers improved performance and communication resource allocation within the regions. The proposed concept is investigated through simulation of real world application scenarios. The simulation results highlight the performance benefit within the region and the increased probability for successful reservation of communication resources. Implementation results show the low area overhead of the proposed hardware support.

Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

Networks-on-Chip (NoC) are the most promising candidates for scalable communication infrastructures in manycore architectures. To ensure scalability, distributed management of communication resources needs to replace centralized approaches. Hence, distributed adaptive routing schemes in combination with selection strategies are used to take semi-optimal routing decisions according to the current NoC utilization. Once these routing decisions are taken for guaranteed service connections, which are established for longer periods, the load situation can change during their lifetime. For such connections taken routing decisions might be poor at a later point in time due to dynamically changing communication workload. The proposed hardware-based mechanism called rerouting reacts on changing load conditions and reallocates existing connections transparently. This balances the NoC load and allows to increase the number of guaranteed service connections. Throughput and delay of existing connections can also be improved by rerouting. The concept is investigated using synthetic traffic patterns and distributed video processing applications. ASIC and FPGA synthesis results are presented to investigate the implementation costs.

Smart Chips for Smart Surroundings - 4S

The overall mission of the 4S project (Smart Chips for Smart Surroundings) was to define and develop efficient flexible, reconfigurable core building blocks, including the supporting tools, for future Ambient System Devices. Reconfigurability offers the needed flexibility and adaptability, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development. In 4S we focused on heterogeneous building blocks such as analogue, hardwired functions, fine and coarse grain reconfigurable tiles and microprocessors. Such a platform can adapt to a wide application space without the need for specialized ASICs. A novel power aware design flow and runtime system was developed. The runtime system decides dynamically about the near-optimal application mapping to the given hardware platform. The overall concept was verified on hardware platforms based on an existing SoC and in a second step with novel silicon. DRM (Digital Radio Mondiale) and MPEG4 Video applications have been implemented on the platforms demonstrating the adaptability of the 4S concept.

Hardware Supported Adaptive Data Collection for Networks on Chip

Managing future many-core architectures with hundreds of cores, running multiple applications in parallel, is very challenging. One of the major reasons is the communication overhead required to handle such a large system. Distributed management is proposed to reduce this overhead. The architecture is divided into regions which are managed separately. The instance managing the region and the applications running within the regions need to collect data for various reasons from time to time, e.g., to collect data for proper mapping decision, to synchronize tasks or to aggregate computation results. In this work, we propose and investigate different strategies for adaptive data collection in meshed Networks on Chip. The mechanisms can be used to collect data within regions, which are defined during run-time in respect of size and position. The mechanisms are investigated while considering delay, NoC utilization and implementation costs. The results show that the selection of the used mechanism depends on the requirements. Synthesis results compare area overhead, timing impact and energy consumption.