Jan Heisswolf

Invasive manycore architectures

This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The necessity for invasive-specific hardware assist functions is analytically shown and their integration into the overall manycore environment is described.

Providing multiple hard latency and throughput guarantees for packet switching networks on chip

In many-core architectures different distributed applications are executed in parallel. The applications may need hard guarantees for communication with respect to latency and throughput to cope with their constraints. Networks on Chip (NoC) are the most promising approach to handle these requirements in architectures with a large number of cores. Dynamic reservation of communication resources in virtual channel NoCs is used to enable quality of service for concurrent communication. This paper presents a router design supporting best effort and connection-oriented guaranteed service communication. The communication resources are shared dynamically between the two communication schemes. The key contribution is a concept for virtual channel reservation supporting different bandwidth and latency guarantees for simultaneous guaranteed service communication flows. Different to state-of-the-art, the used scheduling approach allows to give hard guarantees regarding throughput and latency. The concept enables to adjust the bandwidth and latency requirements of connections at run-time to cope with dynamically changing application requirements. Due to its distributed reservation process and resource allocation it offers good scalability for many-core architectures. The implementation of a router and the required extension of a network interface to support the proposed concept are presented. The software perspective is discussed. An algorithm is presented that is used to establish guaranteed service connections according to the applications bandwidth requirements. Simulation results are compared to state-of-the-art arbitration schemes and show significant improvements of latency and throughput, e.g. for an MPEG4 application. Synthesis results expose the low area overhead and impact on energy consumption which makes the concepts highly attractive for QoS-constraint many-core architectures.

A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling

Networks on Chip are the most promising approach to cope with communication requirements in future many core SoCs. Depending on the executed applications, communication requirements may vary at run-time. Dynamic reservation of communication resources in virtual channel NoCs is an encouraging approach for connection-oriented communication guaranteeing QoS. This paper presents a concept enhancing virtual channel reservation to support different bandwidth and latency guarantees. The used weighted round robin scheduling provides hard guarantees regarding throughput and latency. The proposed router design enables dynamic sharing of communication resources between connectionless Best Effort and connection-oriented Guaranteed Service traffic. Due to decentralized routing and resource management it offers a very good scalability for future many core architectures. Simulation results are obtained from a 10x10 NoC with a cycle accurate SystemC router model. The presented results are compared to existing round robin arbitration schemes and show the advantage of the proposed concept. Synthesis results expose its low area overhead.

A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors

The dynamic run-time complexity of embedded applications is steadily increasing. Currently, only specialized Multiprocessor System-on-Chip (MPSoC) architectures can deliver the required processing power as well as energy efficiency. Although todays MPSoCs incorporate different, potentially reconfigurable cores, their ability to dynamically balance exploitable instruction-, data-, and thread-level parallelism is still very limited. In this paper, we present a novel coarse-grained reconfigurable architecture that can be adapted to operate on different computation granularities and types of parallelism at run time, depending on the applications needs. Our contributions comprise different micro architectural techniques realizing dynamic operation execution for Run-time Scalable Issue Width (RSIW) processor instances. These enable to adapt on demand the issue width of out-of-order RSIW processor instances. Our results show that significant performance improvements can be obtained by our dynamic operation execution technique compared to atomic instruction execution.

Virtual networks -- distributed communication resource management

Networks-on-Chip (NoC) enable scalability for future manycore architectures, facilitating parallel communication between multiple cores. Applications running in parallel on a NoC-based architecture can affect each other due to overlapping communication. Quality-of-Service (QoS) must be supported by the communication infrastructure to execute communication-, real-time- and safety-critical applications on such an architecture. Different strategies have been proposed to provide QoS for point-to-point connections. These strategies allow each node to set up a limited number of connections to other nodes. In this work Virtual Networks (VN) are proposed to enable QoS for regions of a NoC-based architecture. Virtual Networks overcome the limitation of point-to-point connections. A VN behaves like an exclusive physical network. Virtual Networks can be defined and configured during runtime. The size of the VN region and the assigned bandwidth can be adjusted depending on the application requirements. Virtual Networks enable the decoupling of local from global communication. Therefore, the communication of the application mapped into the region is assigned to a Virtual Network established in that specific region. This concept targets packet-switched networks with virtual channels and is realized by an intelligent hardware unit that manages the virtual channel reservation process at system runtime. Virtual Networks can be established and administrated independent of each other, enabling distributed communication resource management. The proposed concept is implemented as a cycle-accurate SystemC simulation model. The simulation results of executing communicating graphs obtained from real application highlight the usefulness of Virtual Networks by showing improved throughput and reduced delay in the respective scenarios. A hardware implementation demonstrates a low impact on area utilization and power consumption.

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS

Networks-on-Chip have shown their scalability for future many-core systems on chip. In real world scenarios, concurrent applications with different QoS requirements affect each other through overlapping communication. Therefore computation resources may not be efficiently utilized because the required communication resources are already occupied. Hence, an efficient resource management strategy is required that ensures fair sharing of communication resources between applications. Decentralized strategies provide better scalability in many-core systems. In this paper, we propose a hardware supported decentralized NoC resource management strategy. Our concept enables to define NoC regions through decentralized reconfigurable resource management policies. It offers improved performance and communication resource allocation within the regions. The proposed concept is investigated through simulation of real world application scenarios. The simulation results highlight the performance benefit within the region and the increased probability for successful reservation of communication resources. Implementation results show the low area overhead of the proposed hardware support.

CAP: Communication Aware Programming

Networks on Chip (NoC) come along with increased complexity from the implementation and management perspective. This leads to higher energy consumption and programming complexity of NoC architectures. This work introduces communication aware programming to address communication resource management and efficient programming of NoC architectures. A programming interface is introduced to express communication requirements at the language level. These requirements are evaluated by an operating system component, which configures the communication hardware accordingly. The proposed concept enables an intuitive use of NoC features like end-to-end connections and Direct Memory Access (DMA). The presented results show that communication aware programming can improve performance and energy consumption.

Architecture design space exploration of run-time scalable issue-width processors

Reconfigurable chip multiprocessors realizing very long instruction word (VLIW) processors of dynamically-scalable issue width enable resource-aware adaptation to diverse processing requirements. The execution performance of such clustered VLIW processors is significantly influenced by different design parameters of the fundamental processing cores. In this paper we present a design space exploration addressing the following design parameters: the register file size, number of issue slots, inter cluster move bandwidth, and latency. We thereby investigate the quantitative performance impact of each parameter as well their interdependency for 18 benchmarks of different processing domains. Our results show that the cluster configuration significantly influences the processing performance: the performance loss compared to theirs unclustered architectures can be as low as 2% but also may exceed 100%.

Hardware prototyping of novel invasive multicore architectures

The sustained advance in technology will enable integrating hundreds of processing cores on a single die in near future. However, it already can be foreseen that the management of the resources of such large systems will not scale in the same way as the hardware using todays entirely software based and centralized management approaches. The invasive paradigm addresses this problem and proposes concepts to enable resource awareness and scalability - especially focusing the resource management perspective - in future multicore systems. These concepts are based on distributed and software-hardware partitioned resource management strategies. High level management decision that are made by software thereby trigger lower level management strategies that are autonomously carried out in hardware. Sufficiently accurate modeling of the overall invasive system is required to study and optimize such a decentralized, software-hardware partitioned control loop where decisions significantly depend on runtime dynamic effects. Software based simulation cannot deliver the required speed or accuracy making FPGA based prototyping of invasive systems necessary. This paper describes our prototyping concepts and discusses possible implementation alternatives for invasive multicore architectures.

Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation

Networks-on-Chip (NoC) are the most promising candidates for scalable communication infrastructures in manycore architectures. To ensure scalability, distributed management of communication resources needs to replace centralized approaches. Hence, distributed adaptive routing schemes in combination with selection strategies are used to take semi-optimal routing decisions according to the current NoC utilization. Once these routing decisions are taken for guaranteed service connections, which are established for longer periods, the load situation can change during their lifetime. For such connections taken routing decisions might be poor at a later point in time due to dynamically changing communication workload. The proposed hardware-based mechanism called rerouting reacts on changing load conditions and reallocates existing connections transparently. This balances the NoC load and allows to increase the number of guaranteed service connections. Throughput and delay of existing connections can also be improved by rerouting. The concept is investigated using synthetic traffic patterns and distributed video processing applications. ASIC and FPGA synthesis results are presented to investigate the implementation costs.