Andreas Zinn

Re-use-centric architecture for a fully accelerated testbench environment

This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without losing compatibility with the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead. The approach itself is hardware independent. To prove the usability of our approach, we verified a hard disc controller on an emulator. With this setup, we achieved a speed-up factor of 5000 versus plain simulation.

A method for accelerating test environments

Functional test environments become more and more important for the design of complex applications and systems. A lot of approaches show the integration of Hardware/Software Cosimulation in those environments. Another focus is the reuse of parts of a testbench for future use. We present a method for accelerating a test environment. Beginning with an existing testbench we explain the distribution of the behavioral functionality, which further remains on the simulator and those parts which can be hardware accelerated The acceleratable parts have to be detected in the testbench description and must be remodelled in a register-transfer level description. Comparisons between simulators and accelerators are stated to show the efficiency of our approach.

Platform-Based Testbench Generation

This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.

Modeling interrupts for HW/SW co-simulation based on VHDL/C coupling

Interaction between hardware and software is often the reason for integration errors when combining both parts. Consequently, Hardware/Software Co-Simulation is required to keep with an increasing demand for an early verification of correct interaction. Using a VHDL/C Coupling, our approach of a modern testbench environment provides the possibility for Co-Simulation. At the beginning interaction was done by executing read and write operations on the software side resulting in CPU bus operations performed by a bus functional model running on a hardware simulator. To reach a higher level of interaction we extended the bus functional model to a peripheral functional model by including an interrupt handler. Accordingly, the hardware is able to react on events from the outside while sending interrupt requests to the software. In consideration of this approach most parts of the final C-software can be tested together with the hardware during an early state of the design flow.

Verifikation und Wiederverwendung (Verification and Re-Use)

Dieser Artikel erläutert verschiedene Aspekte von Wiederverwendung und Verifikation. Dazu wird zunächst der Begriff Verifikation diskutiert. Danach werden besondere Herausforderungen bei der Verifikation von wiederverwendbaren Modulen sowie von Systemen, die aus wiederverwendbaren Modulen zusammengesetzt sind, vorgestellt. Anschließend wird im Abschnitt Verifikations-IP ein Ansatz zur Wiederverwendung in der Verifikation beschrieben, der in verschiedenen Ausprägungen bereits industriell eingesetzt wird. Abschließend wird auf den Einfluss von innerhalb der integrierten Schaltung ablaufender Software eingegangen.