Wolfgang Ecker

Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators

Several leading research groups name hardware generation as the next disruptive productivity improvement after IP-reuse. Metamodeling and code generation have already demonstrated a speedup by a factor 3× for the complete implementation phase of a chip. Furthermore, code size reduction by a factor of 3× was achieved with the hardware generation language (HGL) Chisel.

A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems

Certifying an electrical/electronic system as functionally safe requires a range of analysis and assessment procedures, which must be performed during the different design and manufacturing phases. In the automotive context, the ISO 26262 standard prescribes a set of methods, including FMEDA (Failure Modes, Effects, and Diagnostic Analysis), to evaluate the safety integrity level of the product. FMEDA is a well-established technique in the industry, however, it still demands cumbersome and error-prone manual tasks. In this paper, we present a model-based approach which enhances the FMEDA process for complex safety-related systems and subsequently achieves effort savings reaching 60% in comparison to the manual procedure. This is realized by formalizing the FMEDA structure and applying a database of failure modes derived from safety standards, recognized fault catalogues, and recent project perceptions. The simulation aspect of the approach enables the systematic composition and the automated assembly of component FMEDAs. It provides a new verification capability for FMEDAs in the sense that potential deficiencies or inconsistencies made by safety analysts can be detected and appropriately corrected.

Where formal verification can help in functional safety analysis

Formal techniques seem to be a way to cope with the exploding complexity of functional safety analysis. Here, the overall fault propagation probability to a certain safety-point in the design must be analyzed. As a consequence, the careful verification of the design is no longer sufficient. In addition, the propagation of all possible faults potentially showing up at all of the designs internal nodes must be validated. But this is not only a complexity challenge. Safety standards have a probabilistic view on functional safety analysis results and aspects such as different fault and pattern probability must be considered and related to requirements such as confidence level and maximum FIT rate. Following an overview on verification challenges around functional safety analysis, we introduce our innovative concept on how formal formal techniques can substantially simplify industrial functional safety analysis ows.

Digital Hardware Design Based on Metamodels and Model Transformations

This contribution presents a Model-driven Architecture (MDA) inspired strategy for the automation of digital hardware design starting at specification level and targeting RT-level. This strategy defines a structured approach with is superior to code generation using scripts, print statements or template engines directly targeting ASCII files.

Analog transaction level modeling

Due to the better technology scaling of digital blocks compared to analog blocks, more and more parts of the analog implementation of modern IC designs are shifted to the digital domain, leading to mixed signal designs. However, no verification methodology, that considers the functional verification task of digital and analog blocks holistically, exists so far, whereas many verification methodologies for the digital domain have arisen over time; the newest being the Universal Verification Methodology (UVM) standard [1].

Fast and accurate UML State Chart modeling using TLM + control flow abstraction

The execution speed of classical HW-centric State Charts can be improved by at least one magnitude when migrating from a clock based execution to a transaction event based execution. Applying control flow abstraction, e.g. migrating from transaction event triggers to block transfer triggers, gives a further improvement in execution speed. Timing accuracy is preserved by separation of time and control using a resource model. The paper presents the methodology of control flow abstraction and the implementation consisting of code generation from UML, the resource model control interfaces, and the resource model implementation. An industrial example concludes the paper.