Martin Zambaldi

Re-use-centric architecture for a fully accelerated testbench environment

This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without losing compatibility with the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead. The approach itself is hardware independent. To prove the usability of our approach, we verified a hard disc controller on an emulator. With this setup, we achieved a speed-up factor of 5000 versus plain simulation.

Platform-Based Testbench Generation

This paper presents a new technology that accelerates system verification. In a real life example, we achieved a speed-up of a factor of about 5000. The key for this speed-up is a configurable, synthesizable testbench architecture, which can be completely mapped to emulators or FPGAs. Exploiting generic controllers and re-using protocol-specific stimuli generators combined with topology and microprogram generation is responsible for almost zero overhead compared to behavioral testbenches.

A layered adaptive verification platform for simulation, test, and emulation

This adaptive architecture for structuring testbenches accommodates various models of a design, from transaction to silicon. Moreover, the adapter-based architecture supports the execution of design models on different simulators (high level, RTL, gate level, and switch level), hardware emulators (the testbench runs entirely on the emulator), and even testers. Here, we present a modular, layered testbench (MLTB) approach to building a testbench. This approach is similar to platform-based design. It consists of a generic testbench kernel (TBK), connected through a bus to testbench elements. Our verification platform also satisfies another meaning of platform: a set of connected tools or a powerful tool environment, normally with an attached database, that acts as a platform for verification.

Memory models for the formal verification of assembler code using bounded model checking

The formal verification of assembler code using hardware verification tools requires memory components, which e.g. hold the code itself and the processed data. Since the count of variables to be proven usually rises with both data-size and address-space, complexity boundaries of formal tools can be reached quickly. Since bounded model checking (BMC) always involves a certain time window and therefore the count of memory accesses is limited, it is possible to optimize the applied memory as far as the address-space and the size in the count of gates is concerned. In this paper we introduce various memory models, which decrease the complexity of formal proofs by applying such optimizations. We provide examples of models with limitations either of the address-space or the amount of storable data. Our analysis shows that these models remarkably enhance the performance, while verifying the instruction-set of a given processor-unit with our in-house BMC-Tool

Verifikation und Wiederverwendung (Verification and Re-Use)

Dieser Artikel erläutert verschiedene Aspekte von Wiederverwendung und Verifikation. Dazu wird zunächst der Begriff Verifikation diskutiert. Danach werden besondere Herausforderungen bei der Verifikation von wiederverwendbaren Modulen sowie von Systemen, die aus wiederverwendbaren Modulen zusammengesetzt sind, vorgestellt. Anschließend wird im Abschnitt Verifikations-IP ein Ansatz zur Wiederverwendung in der Verifikation beschrieben, der in verschiedenen Ausprägungen bereits industriell eingesetzt wird. Abschließend wird auf den Einfluss von innerhalb der integrierten Schaltung ablaufender Software eingegangen.