Andrei Vladimirescu

Tunnel field effect transistor with increased ON current, low-k spacer and high-k dielectric

An improved double-gate tunnel field-effect transistor structure with superior performance is proposed. The originality consists in the introduction of a low-k spacer that is combined with a high-k gate dielectric. Numerical simulations demonstrate that the use of the low-k spacer and high-k gate dielectric leads to a high on-current, ION, and reduced subthreshold slope. The proposed structure increases ION by a factor of 3.8 and reduces the subthreshold slope by a factor of 2 compared to other structures described in literature.

A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation

This paper presents a comparative study of sub-32 nm CMOS 6T and 4T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Both independent- and connected-gate operation is analyzed by modulating the drain current with both front and back gate voltages. An improved 4T driver-less (DL) SRAM cell is proposed which takes advantage of the back gate to improve stability in read and retention mode by applying feedback between access transistor and storage node. The results of statistical characterization of read-, retention- and write margins, power and access time are presented for all cells in the presence of process variability.

Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications

In this paper, an ultra-low-leakage TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad memory is proposed. DPSRAM cells are designed using TFETs to reduce the leakage power in the memory array as compared to CMOS. Peripheral circuits are designed using 28nm FDSOI technology to increase speed and to reduce area as compared to full TFET based memories. Performance and stability of the memory is analyzed for different supply voltages to support dynamic voltage frequency scaling (DVFS). Imbalanced single-ended sensing is proposed in the paper and different write-assist techniques are analyzed for the proposed TFET memory cell. In the analysis of TFET DPSRAM bitcell at 1V supply voltage the evaluated noise margins are 114mV and 185 mV for read and write, respectively, with a 5 orders of magnitude reduction in leakage as compared to a similar CMOS bitcell. Results of performance evaluation of the designed 32Kb TFET/CMOS DPSRAM show a gain of up to 79.2% in write speed using write assist at sub-1V supply voltages and less than 1 ns read/write cycle time for more than 1V supply voltages.

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization

This paper presents a methodology for the optimal design of CMOS 6T SRAM ultra-low-power (ULP) bitcells minimizing power consumption under strict stability constraints in all operating modes. An accurate analytical SRAM subthreshold model is developed for characterizing the cell behavior and optimizing its performance. The proposed design approach is demonstrated for an SRAM implemented in a 32nm CMOS UTBB-FDSOI technology. Stable operation in both read and write is obtained for the optimized cell at VDD=0.4V. Moreover, in the optimization process the standby and active power were reduced up to 10x and 3x, respectively.

3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications

This paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while CMOS for periphery. The simulation extractions for power and speed are done including wiring and device parasitic capacitance from 4Kb SRAM designed in 28nm FDSOI CMOS process using MOSFETs & Tunnel FETs (TFETs). The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. A 0.35 fA/bit memory array leakage current was achieved showing a 14x to 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells. Minimum read and write access pulse is evaluated at 1.27ns at sub-1V supply voltage.

Ultra-compact SRAM design using TFETs for low power low voltage applications

This paper presents a hybrid TFET/CMOS SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like the IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while periphery is maintained in standard CMOS. The simulation extractions for power and speed are done including wiring and device parasitics extracted from 4Kb SRAM designed in 28nm FDSOI CMOS process. The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. The memory array leakage current is less than 1 fA/bit at sub-0.5V supply voltages, showing up-to 50x and 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells, respectively. Bitcell area is reduced by 3x in comparison to existing TFET designs. Evaluated static noise margin (SNM) is 100mV for supply voltages range from 0.2V to 0.6V. Minimum read and write access pulse is evaluated at 15ns at 0.45V supply voltage.

A 32nm tunnel FET SRAM for ultra low leakage

This paper describes the applicability of Tunnel FETs to commercial embedded Static Random-Access Memories (SRAM). Numerical device simulations were used first to optimize the performance of the TFET. The optimized TFETs show a steeper subthreshold slope than CMOS leading to a 5 orders of magnitude reduction in standby current. A look-up table model for circuit simulation of the TFET was developed based on characteristics obtained from TCAD simulations. A TFET SRAM cell is proposed and its stability is analyzed. Our novel 8T TFET SRAM cell operates at VDD=1V. The Read and Write Static Noise Margins are evaluated at 120mV and 200mV, with the operation speed of 300MHz and 1GHz in read and write respectively. The cell leakage is less than 10fA at VDD=1V. Our results show that TFETs are excellent candidates for embedded SRAMs due to their Ultra-Low Standby Power (LSTP).

Yield, Power and Performance Optimization for Low Power Clock Network under Parametric Variations in Nanometer Scale Design

Advancing in the nanometer regime, parametric variations has made yield a critical parameter to be included right in the beginning of the design process. Low power circuits have to be designed keeping in mind power consumption, minimum performance levels and yield and find the best compromise between all three. Statistical techniques, Monte Carlo Analysis, using log-normal model has been used to study the effect of parametric variations in leakage dominant 65 nm clock network design. Power supply (Vdd) and threshold voltage (Vth) scaling along with length and device sizing optimization is used to achieve best compromise among power consumption, delay and yield depending on the target application. General guidelines based on final application are given.

Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications

In this paper, we propose a novel TFET Flip-Flop (TFET-FF) designed to address the requirements of ULP (Ultra-Low-Power) applications, like IoT (Internet of Things), while maintaining high performance. The performance of the proposed design in terms of power, area and speed is compared with different flip-flop designs present in literature for MOSFETs, TFETs and FinFETs. The proposed flip-flop supports voltage scaling and works for supply voltages from 0.3V to 0.6V. Leakage is improved by 4 to 7 decades in comparison to state-of-the-art TFET, FinFET and MOSFET designs. With neither feedback for latch implementation nor device stacking, the TFET-FF speed is comparable or exceeds the speed of High-Performance FinFET implementation for VDD = 0.3V/0.5V. The number of transistors used for the proposed TFET-FF is reduced by 50% in comparison to CMOS and FinFET implementations.

Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients

This work presents a comparison of resilience between a 32nm Bulk and a 28nm Fully-Depleted Silicon On Insulator (FDSOI) transistor to heavy ion impacts on the Drain region. The impacts were performed in different transistor locations at different impact angles whereas previous works considered the impact just at a 0 degree angle. This comparison is performed with the device in the off-state using 2D TCAD simulations. The results show a 7.7 times improved resilience of the FDSOI transistor compared to that of Bulk MOSFET.