Andres F. Gomez

An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging

This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.

Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability

Bias Temperature Instability (BTI) has become a major issue for circuit reliability in deeply scaled CMOS technologies. Due to BTI, circuit delay increases as time progress, which may lead to a timing constraint violation. This paper proposes an efficient metric to select the most favorable gates to be resized to enhance circuit reliability. A close analysis is devoted to the main aspects allowing to identify the most favorable gates to be resized. The metric introduces a composited point of view of gate delay sensitivity to channel width sizing, which reflects the sizing impact on the initial gate delay and gate delay degradation. Other parameters are also considered to improve the metric effectiveness. The proposed metric has been applied in some ISCAS85 benchmark circuits along with an iterative gate-selection and gate-sizing procedure. The results show that our proposal is suitable to achieve higher product reliability with minimum area overhead.

A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage

Actually there is a great interest of new methodologies for reducing the power consumption of integrated circuits. Power consumption raises the operating temperature that devices experience. Consequently, circuit reliability is affected due to temperature-dependent mechanisms like Negative Bias Temperature Instability (NBTI). This paper proposes a methodology based on dual supply voltage technique to mitigate delay degradation due to NBTI for applications requiring to reduce the power consumption. In the proposed methodology, the low voltage supply is slightly lower than the high (nominal) voltage supply. Therefore, voltage level converters are not required. A gate metric is proposed to estimate the benefit of lowering the supply voltage of a gate on circuit power consumption and delay degradation. The results show that NBTI-induced delay degradation and power consumption are reduced at some small delay penalty. This leads to circuits with lower power consumption and higher reliability.

Circuit performance optimization for local intra-die process variations using a gate selection metric

Process variations are imposing strong limits to performance of digital circuits at gigascale integration; they are classified in two types: inter-die and intra-die variations. Moreover, intra-die variations, which were ignored in the past, now have become significant. The present work proposes a statistical performance optimization methodology using a gate selection metric to enhance performance of digital integrated circuits in the presence of local intra-die process variations. The gate selection metric allows to select those gates to be re-sized for improving circuit performance at a lower area cost. This selection metric allows to optimize the circuit behavior using Lagrange method. The obtained results on ISCAS benchmark circuits show the benefits of the proposed methodology. The proposed optimization methodology allows to increases yield leading to better revenue.

A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging

Bias Temperature Instability (BTI) has become a major aging issue for circuit lifetime reliability in deeply scaled CMOS technologies. Due to BTI, circuit delay increases as time progress, which may lead to a timing constraint violation before the end of the expected lifetime. This paper proposes a new sizing approach to mitigate BTI induced delay degradation of digital circuits. The approach is based on the observation that the delay sensitivity to transistor sizing of a digital gate is composed by a nominal delay sensitivity and a delay degradation sensitivity components. By exploiting the differences between these two components, one can size some gates in the critical paths of a circuit, in such way that the delay degradation due to BTI is reduced while the nominal delay remains nearly unchanged. By using our sizing approach, the reduction of delay degradation allows to further extend the lifetime of a circuit with negligible area and power overhead.

Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects

Conventional clock guardbanding to assure a circuit’s reliable operation under device aging due to NBTI/PBTI and process variations introduce significant performance loss in modern nanometer circuits. Dynamic Frequency Scaling (DFS) is a more efficient technique that allows us to adjust the system clock frequency according to the process condition and aging deterioration of the circuit. At the design phase, the DFS technique requires the identification of the logic paths to be monitored to introduce the required circuitry to monitor their delay. However, critical path identification is a complex problem due to three major challenges: (1) The critical paths of the circuit depend on the stress duty cycle of the devices, which are unknown in advance at design phase; (2) the critical paths of the circuit depend on the process parameters variations, whose impact on delay depend on the spatial correlation due to proximity at the circuit layout; and (3) the critical paths reordering probability may change over time due to aging. This article presents a methodology for efficient selection of the critical paths to be monitored under a DFS framework, addressing the aforementioned challenges. Experimental results on ISCAS 85/89 benchmark circuits show the feasibility of the proposed approach to select a restricted path set while providing reliable aging monitoring.

Critical path selection under NBTI/PBTI aging for adaptive frequency tuning

Critical Paths Monitoring is an efficient technique to overcome transistor aging. A methodology to select critical paths to be monitored at design phase is proposed. A spatial correlation approach is used to perform Statistical Timing Analysis at design phase. Critical paths are selected for various aging workload profiles to avoid worst-case assumptions. The results show that up to 16x less paths are selected compared to path selection using worst-case aging. Moreover, the selected paths match well with those selected using spatial correlation extracted from final circuit layout.

Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations

Abstract Resistive-open defects in Static Random Access Memories (SRAMs) represent an important challenge for manufacturing test in submicron technologies as they may be masked by process variations, which in turn increases the number of test escapes. This paper evaluates the effectiveness of a hardware-based test approach that compares the current consumption of neighboring SRAM cells to detect resistive-open defects. The proposed approach is validated and its fault detection capabilities are analyzed for different defect sizes and taking into account process variations effects. Finally, the paper provides an evaluation of the minimum detectable resistive-open defect size for the proposed hardware-based approach under process variations effects.