Andrew Beaumont-Smith

Parallel prefix adder design

The paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0.25 /spl mu/m CMOS technology for a range of adder widths as a comparative study.

A GaAs 32-bit adder

Presents a new parallel GaAs 32-bit adder based on a combination of the Han-Carlson (1987) and Kowalczuk (1991) parallel adders. GaAs is particularly sensitive to loading, so our aim was to reduce the wire lengths and the fanout of each gate. Our architecture achieves this by significantly reducing the number of cells in the carry tree while not significantly reducing its speed. The delay of the adder fabricated in 0.6 /spl mu/m MESFET GaAs technology was measured at 1.27 ns, with a power dissipation of 114 mW at 0.9 V. The area is 0.3 mm/sup 2/ with a maximum density of 8000 transistors/mm/sup 2/. The figure of merit is 0.21 /spl mu/W/MHz/spl middot/gate.

Results of A/D converter compensation with a VLSI chip

Error table compensation is one technique that can be used to improve the spurious free dynamic range of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, some additional on chip circuits, and a lookup table that is stored in external memory. The 10 GOPS transversal filter differentiator chip was designed and fabricated in a 0.35 /spl mu/m CMOS process, has programmable tap weights, and can operate at a maximum clock rate of 200 MHz. The results of this paper show that this error table compensation system is capable of providing up to 13 dB improvement in the dynamic range of typical high speed A/D converters. This may result in more reliable detection of weak signals of interest.

Biologically inspired obstacle avoidance: a technology-independent paradigm

With regard to obstacle avoidance, a paradigm shift from technology centered solutions to technology independent solutions is taking place. This trend also gives rise to a shift from function specific solutions to multifunctional solutions. A number of existing approaches are reviewed and a case study of a biologically inspired insect vision model is used to illustrate the new paradigm. The insect vision model leads to the realization of a sensor that is low in complexity, high in compactness, multifunctional and technology independent. Technology independence means that any front end technology, resulting in either optical, infrared or mm wave detection, for example, can be used with the model. Each technology option can be used separately or together with simple data fusion. Multifunctionality implies that the same system can detect obstacles, perform tracking, estimate time-to-impact, estimate bearing, etc. and is thus non-function specific. Progress with the latest VLSI realization of the insect vision sensor is reviewed and gallium arsenide is proposed as the future medium that will support a multifunctional and multitechnology fusion of optical, infrared, millimeter wave, etc. approaches. Applications are far reaching and include autonomous robot guidance, automobile anti-collision warning, IVHS, driver alertness warning, aids for the blind, continuous process monitoring/web inspection and automated welding, for example.

An array processor architecture for support vector learning

Support vector training requires the evaluation of a quadratic programming (QP) problem which is computationally intensive. In addition, the size of the QP is dependent on the number of training samples and may exceed the memory size. This paper presents a fast parallel implementation of the SVM on an array processor which is optimised for matrix operations. A decomposition algorithm is used to break large scale support vector problems into a fixed size block for efficient processing in the array.

10-GOPS transversal filter and error table compensator

A cascadable 10GOPS transversal filter chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti- symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4 - 2 compressors to reduce the transistor count. The chip was fabricated in a 0.35 micrometer CMOS process, measures 3.1 X 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz (200 MSa/s throughput). An error table compensator system using a lookup table has been built using the transversal filter programmed as a wideband differentiator with some additional on chip circuits including delays and an adder. An external memory stores the error table. The error table technique is capable of providing between 7 to 15 dB improvement in the dynamic range of typical 100 Ms/s A/D converters. An application to pulse shaping of high chip rate spread spectrum signals is also discussed.