Michael J. Liebelt

An energy efficient rate selection algorithm for voltage quantized dynamic voltage scaling

The paper presents a highly energy efficient alternative algorithm to the conventional workload averaging technique for voltage quantized dynamic voltage scaling. This algorithm incorporates the strengths of the conventional workload averaging technique and our previously proposed Rate Selection Algorithm, resulting in higher energy savings while minimizing the buffers size requirement and improving the overall system stability by minimizing the number of voltage transitions. Our experimental work using the Forward Mapped Inverse Discrete Cosine Transform computation (FMIDCT) as the variable workload computation, nine 300-frame MPEG-2 video sequences as the test data, and a 4-level voltage quantization shows that our algorithm produces better energy savings in all test cases when compared to the workload averaging technique, and the maximum energy saving for the test cases was 23%.

Improving binary compatibility in VLIW machines through compiler assisted dynamic rescheduling

One of the main problems that prevents extensive use of VLIW architectures for non-numeric programs is lack of object code (or binary) compatibility among different implementations of the same architecture. This is due to exposing all architectural features to generate code at compile time. New features of a VLIW machine may lead to incorrect results by executing the code compiled for the older machine. In this paper, a new approach to overcome this problem is presented, which we call dynamic VLIW generation (DVG). It is performed with the help of code annotation provided by the compiler, to reduce the complexity of the required hardware. In the DVG technique, operations are rescheduled for the new machine at the time of instruction cache miss repair. In this way, the rescheduler hardware is not located in the execution pipeline engine avoiding potentially longer cycle times. To simplify the dependency checking hardware, dependency information is encoded for each operation at compile time. This information can be combined into the final binary code, or may be provided as a separate file, which can be loaded into memory at execution time by the OS loader. In this technique operations can be rescheduled speculatively and a mechanism is presented to prevent destroying the contents of live registers. Experimental results show that the performance of rescheduled code using the DVG technique is about 10% worse than code compiled directly for the target processor.

High girth column-weight-two LDPC codes based on distance graphs

LDPC codes of column weight of two are constructed from minimal distance graphs or cages. Distance graphs are used to represent LDPC code matrices such that graph vertices that represent rows and edges are columns. The conversion of a distance graph into matrix form produces an adjacency matrix with column weight of two and girth double that of the graph. The number of 1s in each row (row weight) is equal to the degree of the corresponding vertex. By constructing graphs with different vertex degrees, we can vary the rate of corresponding LDPC code matrices. Cage graphs are used as examples of distance graphs to design codes with different girths and rates. Performance of obtained codes depends on girth and structure of the corresponding distance graphs.

Interconnection Network for Structured Low-Density Parity-Check Decoders

Most structured codes use the group-and-permute design approach in which rows and columns are divided into groups of the same size. Row/column groups and individual row-column are connected by some permutation. A general group-and-permute decoder requires an interconnection network for group-to-group communication. In this paper we suggest the use of self-routed Benes networks based on the communication pattern of LDPC codes. Bipartite edge coloring is used to schedule messages such that there are no switch network output conflicts. The looping routing algorithm for Benes networks is used to compute switching codes. Both scheduling information and switching codes are pre-computed and stored for each design code since they do not change in the lifetime of the code

Elliptic curve digital signature algorithm over GF(p) on a residue number system enabled microprocessor

We describe a residue number system (RNS) implementation of the 192-bit elliptic curve digital signature algorithm over GF(p). It uses a Tensilica Xtensa LX2.1 microprocessor core with hardware extensions to improve the performance of RNS operations. The low power and small area of the enhanced Xtensa LX2.1 core make it suitable for smart cards. This implementation is the first to use the RNS for elliptic curve cryptography on a sequential microprocessor. The RNS-enabled microprocessor performs a 192-bit point multiplication in approximately 2 million clock cycles, a performance that compares well to other minimally enhanced elliptic curve cryptography implementations.

Quasi-cyclic LDPC codes of column-weight two using a search algorithm

This article introduces a search algorithm for constructing quasi-cyclic LDPC codes of column-weight two. To obtain a submatrix structure, rows are divided into groups of equal sizes. Rows in a group are connected in their numerical order to obtain a cyclic structure. Two rows forming a column must be at a specified distance from each other to obtain a given girth. The search for rows satisfying the distance is done sequentially or randomly. Using the proposed algorithm regular and irregular column-weight-two codes are obtained over a wide range of girths, rates, and lengths. The algorithm, which has a complexity linear with respect to the number of rows, provides an easy and fast way to construct quasi-cyclic LDPC codes. Constructed codes show good bit-error rate performance with randomly shifted codes performing better than sequentially shifted ones.

A rate selection algorithm for quantized undithered dynamic supply voltage scaling

In this paper we propose a novel rate calculation algorithm called quantized rate selection (QRS) for quantized undithered dynamic supply voltage scaling (DSVS) systems. The algorithm monitors the total buffered workload, and where possible selects a rate value equal to a quantized rate value. At quantized rate values, energy dissipation of quantized DSVS systems approaches continuous voltage level DSVS systems. Our experimental work on FMIDCT computation using nine video sequences and a 4-level quantized undithered system shows that additional energy savings of 1.4% to 18.5% can be achieved from QRS, compared to the existing averaging technique.

Energy minimization in dynamic supply voltage scaling systems using data dependent voltage level selection

In this paper we propose a workload distribution based quantized voltage level selection method called Data Dependent Level Selection (DDLS) for minimizing energy in dynamic supply voltage scaling systems. In previous works, the voltage levels have been selected by dividing the maximum normalized workload by the number of quantized voltage levels. The existing techniques place no emphasis on workload characteristics of data in selecting quantized voltage levels. Our DDLS technique is a workload distribution based technique that selects the minimum energy yielding quantized voltage levels for a given data sequence. For the 300-frame Akiyo video sequence, our DDLS analysis shows that up to 55% of energy savings can be obtained compared to the existing methods.

ECSTAC: a fast asynchronous microprocessor

This paper introduces some of the principal design issues encountered in the development of a prototype asynchronous microprocessor using a two-phase communication strategy. These issues include the control of the processor pipeline, register tagging, branch techniques, and the implementation of caches. The arbitration and synchronisation methods employed in the design are discussed, and expected performance figures based on block simulation results are given.

Two-phase asynchronous pipeline control

In this paper the potential speed and power efficiency of two-phase asynchronous systems operating under a bounded-delay model are explored. It is shown that two-phase bounded-delay systems can significantly outperform four-phase approaches published to date. The design of a prototype microprocessor using this two-phase approach is then described, and preliminary results are presented.