Andrew Bicksler

Effects of Source Diffusion on SILC and Cycling-Induced Charge Loss in Source-Bias Erase Flash Cells

A recent report reveals that in source-bias erase flash cells, light source doping can cause room temperature erratic charge loss after program/erase cycling. In this paper, we present tunnel oxide hole trapping and stress induced leakage current (SILC) measurements under source-bias erase stress conditions, in cell structures with different source doping profiles. Data suggests the deep depletion in cell source during erase causes hole trapping in tunnel oxide above the source diffusion, which is responsible for the room temperature charge loss after P/E cycling for light doping source

3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation. This paper reviews the main features of GIDL-assisted body biasing and GIDL optimization methods ensuring the best erase effectiveness and variability control. Finally, the excellent reliability of the selector gate devices over Program/Erase cycles is demonstrated, proving the reliability of this technique.