Akira Goda

A Program Disturb Model and Channel Leakage Current Study for Sub-20 nm nand Flash Cells

We have developed a program-disturb model to characterize the channel potential of the program-inhibited string during NAND flash cell programming. This model includes cell-to-cell capacitances from 3-D technology computer-aided design simulation and leakage currents associated with the boosted channel. We studied the program-disturb characteristics of sub-30-nm NAND cells using a delayed programming pulse method. The simulation results agree with the experimental data very well and show quantitative impacts of junction leakage current, band-to-band tunneling (BTBT) current, Fowler-Nordheim tunneling current, and channel capacitance on the program disturb. We further discuss the cell-scaling trend and identify that the BTBT current can be a dominant mechanism for the program disturb of sub-20-nm NAND cells.

Scaling directions for 2D and 3D NAND cells

This paper describes NAND cell scaling directions for 20nm and beyond. Many of the 2D NAND cell scaling challenges can be resolved by a planar floating gate (FG) cell. Scaling directions and key technology requirements for 3D NAND are also discussed.

Resolving discrete emission events: A new perspective for detrapping investigation in NAND Flash memories

We report the first experimental evidence of discrete threshold-voltage transients on high-density NAND Flash arrays during post-cycling data retention. Proper choice of experimental conditions eliminates the impact of averaging effects and disturbs on the transients, enabling clear detection of single charge emission events from/to the tunnel oxide of sub-30nm NAND Flash cells. A stochastic model for the discrete emission process was developed from experimental data, demonstrating that number fluctuation of charges trapped in the tunnel oxide and the statistical nature of their emission dynamics strongly affect the post-cycling data retention performance of the arrays. These results pave the way for further analyses of NAND Flash reliability, where the behavior of single electrons and defects can be monitored and facilitate detailed assessments of the fundamental scaling challenges arising from the discrete nature of charge trapping/detrapping.

Extreme Short-Channel Effect on RTS and Inverse Scaling Behavior: Source–Drain Implantation Effect in 25-nm nand Flash Memory

In 25-nm NAND Flash memory, source-drain implantation conditions significantly affect random telegraph signal (RTS). In this extremely short gate length regime, RTS is proportional to the effective gate length (Leff) which exhibits an “inverse scaling effect.” Process simulation reveals that the laterally straggled and diffused As atoms from source/drain are sufficient to change the effective boron concentration even in the center of the channel which changes macroscale potential profile for the short-channel effect but also changes RTS by modulating random discrete dopant (RDD) effect. This result continues up to 10 000 program/erase cycles which indicates that the defect generation rate for RTS is not changed under the relevant doping conditions. Modeling of the source-drain dopant distribution must include atomistic simulation for accurate prediction of the RDD effect in NAND Flash memory below 30 nm.

Fitting Cells Into a Narrow

This paper presents an in-depth comparative analysis of the major physical constraints to the width of the threshold-voltage distribution of a state-of-the-art NAND Flash array. The analysis addresses both time-0 placement by program-and-verify algorithms on fresh and cycled arrays and distribution widening during idle/bake periods. Results allow to identify how each physical effect impacts the threshold-voltage distribution as a function of array program conditions, temperature, cycling, and duration of idle/bake periods, providing clear hints for the design of next generation technology nodes.

V_{T}

We report the impact of tunnel oxide nitridation (TON) on the evolution of random telegraph signal (RTS) and quick electron detrapping (QED) and investigate their microscopic origin. Applying nitridation at the SiO2/Si interface increases both Fermi level (RTS) and general midgap (QED) defects in fresh devices. However, it slows down additional defect generation and demonstrates improvement after severe program/erase cycling. Results from low-frequency 1/f noise indicate that TON aggravates RTS for high energy defects but hardens low energy defects, resulting in improved postcycled RTS. The suggestive defect chemistry is that strong Si-N bonding replaces relatively stable (but distorted) Si-O bonding, rather than passivating high energy dangling bonds. The Si-N bonding also causes more interface bonds to break, reducing strain and improving immunity against Fowler-Nordheim stress.

Interval: Physical Constraints Along the Lifetime of an Extremely Scaled NAND Flash Memory Array

In sub-40-nm flash memory, random discrete dopant (RDD) effect modulates post program/erase (P/E) cycling Vt instabilities through quick electron detrapping (QED) as well as random telegraph signal (RTS). In this letter, for the first time, we discuss the QED phenomenon and its physical origin by comparison with RTS phenomenon. P/E cycling stress not only aggravates the RTS but also generates the new phenomenon of QED which results from transiently trapped charges at near-interface defects during program. By applying a new test algorithm, we could successfully extract the QED component from RTS, both of which are modulated by RDD effect and worsen tail bits in multilevel-cell flash memory.

Tunnel Oxide Nitridation Effect on the Evolution of

This paper reviews the recent historical trends of the NAND Flash technology, highlighting the evolution of its main parameters and explaining what allowed it to become not only the most important integrated solution for nonvolatile storage of high volumes of data but also a strong rival eroding the market share of hard-disk drives. The scaling trend followed by planar arrays will be discussed with close attention, along with the major physical constraints impacting the performance and the reliability of modern deca-nanometer technologies. This will make clear why the development of further planar nodes with feature size below ~15 nm, representing today’s state of the art, can be considered less favorable than turning all the efforts toward the integration of 3-D arrays. The most promising 3-D architectures will then be reviewed, discussing their benefits and issues and addressing the impact of the change of the integration paradigm from the standpoint of the major NAND applications.

V_{t}

We conduct a thorough investigation of random telegraph noise (RTN) dependence on program/erase and read/bake conditions in state-of-the-art 1X and 2X Flash NAND technologies. We demonstrate that RTN depends only on the cycle number and not on the program level or cycling pattern. Moreover, if the cumulative distribution of RTN is considered, a negligible temperature dependence appears, in apparent contrast with thermal activation of single-trap time constants. RTN appears also to be independent of the read and bake temperature, although a slight asymmetry in the distribution tails is induced by charge detrapping. A Monte Carlo model is also presented to account for the experimental observations.

Instabilities (RTS/QED) and Defect Characterization for Sub-40-nm Flash Memory

Introduction: Random telegraph noise (RTN) during read and charge detrapping during data retention cause time dependent threshold voltage (VT) fluctuations in NAND flash memories [1-9]. This paper reviews and discusses the physics of these phenomena and the impact on NAND array reliability based on characteristics of aggressively scaled 2D planar NAND cells [10][11]. The discussion is further extended to 3D NAND.