Andrew Carlson

Large-Scale SRAM Variability Characterization in 45 nm CMOS

Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements. A test chip is implemented in a 45 nm CMOS process. Large-scale SRAM read/write metrics are measured and compared against conventional SRAM stability metrics. Results show excellent correlation to conventional SRAM read/write metrics as well as VMIN measurements near failure.

SRAM Read/Write Margin Enhancements Using FinFETs

Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve control and reduce short channel effects. Among the likely candidates, FinFETs are the most attractive option because of their good scalability and possibilities for further SRAM performance and yield enhancement through independent gating. The enhancements to read/write margins and yield are investigated in detail for two cell designs employing independently gated FinFETs. It is shown that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. The write-ability of the cell can be improved through the use of pull-up write gating (PUWG) with a separate write word line (WWL). The benefits of these two approaches are complementary and additive, allowing for simultaneous read and write yield enhancements when the PGFB and PUWG designs are used in combination.

Large-scale read/write margin measurement in 45nm CMOS SRAM arrays

Distributions of read and write noise margins in large CMOS SRAM arrays are investigated by directly measuring the bit-line current during bitline / wordline (write) or cell supply (read) voltage sweep in a 768 Kb 45 nm CMOS SRAM test-chip. Good correlation between write/read margin estimates through the bit-line measurements and the DC read SNM (RSNM) and IW measurements in small on-chip SRAM macros with wired-out storage nodes are demonstrated. Four common writeability metrics are correlated and compared. Array-level characterization of SRAM cell read stability and writeability allow fast and accurate characterization of high-density SRAM arrays is scalable for capturing up to 6 standard deviations of parameter variations.

FinFET SRAM with Enhanced Read / Write Margins

In this work, the impact of this pass-gate feedback (PGFB) technique on cell write-ability is examined, and gate workfunction (Phim) tuning for optimization of the trade-off with read margin is discussed. To further improve cell write-ability, the p-channel pull-up devices can also be operated in BG mode, with their back gates driven by a separate write word line. This pull-up write gating (PUWG) technique is effective for maintaining larger than 6 standard deviations yield down to 0.4V VDD without area penalty, making FinFET-based 6-T SRAM compelling for high-density memory applications

Negative and iterated spacer lithography processes for low variability and ultra-dense integration

Variation in the critical dimension (CD) of a transistor is a primary concern for advanced lithography. Because variation from sources such as corner rounding or line edge roughness does not scale with CD, variability in transistor performance increases with scaling and may impact the timing or even the functionality of critical circuits such as static random access memories (SRAM) and ring oscillators. Spacer lithography is an attractive patterning method for future technology nodes, because its use of a very uniform and controllable chemical vapor deposition (CVD) step allows for the definition of very narrow lines with low variation and reduced pitch1,2. In practice, however, the possible pitch reductions are limited by the need for conventional lithography to produce negative features (e.g., trenches and holes) and increasing CD variability with iterated spacer processing. In this work, an extension to spacer lithography is presented to overcome these limitations. Negative features down to 30nm in width are fabricated using spacer-defined features. A multi-tiered hard mask process is also presented to enable eight-fold pitch reduction with no increase in CD variation. In combination, these processes enable ultra-dense circuit integration for regular layouts.

Compensation of systematic variations through optimal biasing of SRAM wordlines

Increasing process variability is slowing SRAM scaling by reducing both read and write margins. Existing techniques to compensate for systematic variations optimize cell stability with excessive penalty to writeability. To maximize overall yield, a sensor circuit is presented that optimizes the read / write tradeoff in the presence of process, voltage, and temperature variations. Sensors implemented in a low-power 45 nm test chip adjust the wordline voltage to track changes in the optimal value within 30 mV over the entire range of operation.

Low-variability negative and iterative spacer processes for sub-30-nm lines and holes

Variation in the critical dimension (CD) of a transistor is a primary concern for advanced lithography. Because variation from sources such as corner rounding or line edge roughness does not scale with CD, variability in transistor performance increases with scaling and may impact the timing or even the functionality of critical circuits such as static random access memories (SRAM) and ring oscillators. Spacer lithography is an attractive patterning method for future technology nodes, because its use of a very uniform and controllable chemical vapor deposition (CVD) step allows for the definition of very narrow lines with low variation and reduced pitch. In practice, however, the possible pitch reductions are limited by the need for conventional lithography to produce negative features (e.g., trenches and holes) and increasing CD variability with iterated spacer processing. In this work, an extension to spacer lithography is presented to overcome these limitations. Negative features down to 30 nm in width are fabricated using spacer-defined features. A multitiered hard mask process is also presented to enable eight-fold pitch reduction with no increase in CD variation. In combination, these processes enable ultradense circuit integration for regular layouts.

SRAM yield and performance enhancements with tri-gate bulk MOSFETs

Multi-gate devices are expected to enable continued scaling beyond the 32nm node in part due to their improved gate control of the channel versus planar MOSFETs. Static random access memory (SRAM) scaling, which requires increasing design margins despite decreasing layout area, may motivate the transition to a multi-gate architecture. Tri-gate bulk devices are an attractive multi-gate option because of their high compatibility with existing circuit designs and processes. In this work. SRAM cell simulations are used to quantify the expected yield improvements and design tradeoffs with tri-gate devices. We show that up to two standard deviations (sigma) of yield enhancement can be expected for both read and write margins, without penalty to cell area or access time. The tri-gate SRAM cell can be further optimized to simultaneously reduce cell area and minimum operating voltage, Vmin.

Tri-gate bulk MOSFET design for improved robustness to random dopant fluctuations

Atomistic 3D device simulations of 20nm-gate-length planar vs. tri-gate bulk MOSFETs with identical nominal retrograde-well and source/drain doping profiles show that the tri-gate structure is more robust to random dopant fluctuation (RDF) effects, i.e. threshold voltage (VTH) lowering and variation. VTH lowering is verified to be due primarily to channel/well RDF. For the tri-gate bulk MOSFET, VTH adjustment via tuning of the doping depth provides for reduced variability, as compared with tuning of the channel/well dose.