Kanghoon Jeon

Si tunnel transistors with a novel silicided source and 46mV/dec swing

We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46mV/dec and high ION/IOFF ratio (∼108) and the experiment was successfully repeated after two months. Its superior operation is explained through simulation. For the first time convincing statistical evidence of sub-60mV/dec SS is presented. More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data.

Prospect of tunneling green transistor for 0.1V CMOS

Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8″ wafers. Large ION at low VDD are possible according to TCAD simulations but awaits verification. VDD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound semiconductors.

Low-voltage green transistor using ultra shallow junction and hetero-tunneling

A novel hetero-tunnel transistor (HtFET) with a heterostructure and ultra shallow junction parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

A Low Voltage Steep Turn-Off Tunnel Transistor Design

Abstract —A new tunneling transistor structure is introduced that offers several advantages over prior designs. Notably, tunneling area is substantially increased. Turn on/off swing is improved by engineering doping profile to ensure tunneling initiates in high electric field region. TCAD simulations explore the critical design considerations. The concept of heterojunction tunneling is introduced as a means to achieve low effective band gap and low voltage operation for the design in consideration. I. I NTRODUCTION Increasing power consumption presents a major problem for future ICs. A transistor that can operate below 0.5 V supply is highly desirable. Maintaining large I on /I off ratio at such low V dd is a challenge for MOSFET given the 60 mV/decade subthreshold swing limit. This limit governs the turn off/on of any device based on flow of carriers over an energy barrier. Band-to-band tunneling (BTBT) is one process not subject to this limitation. Researchers have long explored the BTBT transistor [1-2]. However, all have relied on the same basic structure -- the gated PN diode. This conventional structure for an n-type FET is shown in Fig. 1. The location of tunneling is indicated by the arrow at the edge of the source region. The transistor “turns on” when the gate voltage exceeds the overlap voltage, V

SiGe CMOS on (110) channel orientation with mobility boosters : Surface orientation, channel directions, and uniaxial strain

We report a comprehensive study of surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS. On a (110) surface, SiGe nMOS demonstrates a higher electron mobility than Si (110) nMOS. The hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain. Results obtained in this work advance the integration technique of high mobility CMOS on a single SiGe (110)<110> channel orientation to enhance overall performance without the process complexity associated with hybrid channel CMOS approaches.

Sub-60nm Si tunnel field effect transistors with I on >100 µA/µm

Si-tunneling field effect transistors (TFETs) with a record I<inf>on</inf> >100 µA/µm and high I<inf>on</inf>/I<inf>off</inf> ratio (> 10⁵) at V<inf>ds</inf>=1V are reported. Using an optimal spike and millisec flash anneal coupled with an engineered source-gate overlap through a gate-last process, Si TFETs have been demonstrated with 10 to 1000 times greater current than previously reported. The devices exhibit negative differential resistance and temperature dependencies consistent with band-to-band tunneling and current characteristics in excellent agreement with 2D TCAD simulations.

Tri-gate bulk MOSFET design for improved robustness to random dopant fluctuations

Atomistic 3D device simulations of 20nm-gate-length planar vs. tri-gate bulk MOSFETs with identical nominal retrograde-well and source/drain doping profiles show that the tri-gate structure is more robust to random dopant fluctuation (RDF) effects, i.e. threshold voltage (VTH) lowering and variation. VTH lowering is verified to be due primarily to channel/well RDF. For the tri-gate bulk MOSFET, VTH adjustment via tuning of the doping depth provides for reduced variability, as compared with tuning of the channel/well dose.

Low-voltage green transistor using hetero-tunneling

A novel hetero-tunnel transistor (HtFET) with a heterostructure parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling Vdd down to 0.2 V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.

ON-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained Si 0.5 Ge 0.5 Quantum-Well pMOSFET Along 110 and 100 Channel Directions

pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.

Comprehensive Study of Quasi-Ballistic Transport in High-

We study quasi-ballistic transport in nanoscale high-κ/metal gate nMOSFETs based on radio-frequency (RF) <i>S</i>-parameter analysis. An RF <i>S</i>-parameter-based simple experimental methodology is used for direct extraction of device parameters (i.e., <i>L</i>_eff, <i>R</i>_sd, and <i>C</i>_inv) and the effective carrier velocity v_eff from the targeted short-channel devices. Furthermore, an analytical top-of-the-barrier model, which self-consistently solves the Schrödinger-Poisson equations, is used to determine the ballistic carrier velocity <i>v</i>_inj at the top of the barrier near the source. Based on the results of the experimental extraction and analytical calculations, backscattering coefficient <i>r</i>_sat and ballistic ratio <i>BR</i>_sat are calculated to assess the degree of the transport ballisticity for nMOSFETs. It is found that conventional high-κ/metal gate nMOSFETs will approach a ballistic limit at an effective gate length <i>L</i>_eff of approximately 7 nm.