Roland T. Knaack

Testing method for FIFOS

Circuit and method for instruction controllable slewrate of bit line driver

Parity generation and check circuit and method in read data path

Multiple word width memory array clocking scheme for reading words from a memory array

Multiple frequency memory array clocking scheme for reading and writing multiple width digital words

Programmable read-write word line equality signal generation for FIFOs

Output buffer circuit and method having improved access

Testing method for devices with status flags

Redundancy method and circuit for self-repairing memory arrays

Clocking scheme for independently reading and writing multiple width words from a memory array