Andrey V. Mezhiba

Scaling trends of on-chip power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.

Power Distribution Networks in High Speed Integrated Circuits

1. Introduction.- 1.1 Evolution of integrated circuit technology.- 1.2 Evolution of design objectives.- 1.3 The problem of power distribution.- 1.4 Deleterious effects of power distribution noise.- 1.4.1 Signal delay uncertainty.- 1.4.2 On-chip clock jitter.- 1.4.3 Noise margin degradation.- 1.4.4 Degradation of gate oxide reliability.- 1.5 Book outline.- 2. Inductive Properties of Electric Circuits.- 2.1 Definitions of inductance.- 2.1.1 Field energy definition.- 2.1.2 Magnetic flux definition.- 2.1.3 Partial inductance.- 2.1.4 Net inductance.- 2.2 Variation of inductance with frequency.- 2.2.1 Uniform current density approximation.- 2.2.2 Inductance variation mechanisms.- 2.2.3 Simple circuit model.- 2.3 Inductive behavior of circuits.- 2.4 Inductive properties of on-chip interconnect.- 2.5 Summary.- 3. Properties of On-Chip Inductive Current Loops.- 3.1 Introduction.- 3.2 Dependence of inductance on line length.- 3.3 Inductive coupling between two parallel loop segments.- 3.4 Application to circuit analysis.- 3.5 Summary.- 4. Electromigration.- 4.1 Physical mechanism of electromigration.- 4.2 Electromigration-induced mechanical stress.- 4.3 Steady state limit of electromigration damage.- 4.4 Dependence of electromigration lifetime on the line dimensions.- 4.5 Statistical distribution of electromigration lifetime.- 4.6 Electromigration lifetime under AC current.- 4.7 Electromigration in novel interconnect technologies.- 4.8 Designing for electromigration reliability.- 4.9 Summary.- 5. High Performance Power Distribution Systems.- 5.1 Physical structure of a power distribution system.- 5.2 Circuit model of a power distribution system.- 5.3 Output impedance of a power distribution system.- 5.4 A power distribution system with a decoupling capacitor.- 5.4.1 Impedance characteristics.- 5.4.2 Limitations of a single-tier decoupling scheme.- 5.5 Hierarchical placement of decoupling capacitance.- 5.6 Resonance in power distribution networks.- 5.7 Full impedance compensation.- 5.8 Case study.- 5.9 Design considerations.- 5.9.1 Inductance of the decoupling capacitors.- 5.9.2 Interconnect inductance.- 5.10 Limitations of the one-dimensional circuit model.- 5.11 Summary.- 6. On-Chip Power Distribution Networks.- 6.1 Styles of on-chip power distribution networks.- 6.1.1 Basic structure of on-chip power distribution networks.- 6.1.2 Improving the impedance characteristics of on-chip power distribution networks.- 6.1.3 Evolution of power distribution networks in Alpha microprocessors.- 6.2 Allocation of on-chip decoupling capacitance.- 6.2.1 Types of on-chip decoupling capacitance.- 6.2.2 Allocation strategies.- 6.2.3 On-chip switching voltage regulator.- 6.3 Die-package interface.- 6.4 Other considerations.- 6.5 Summary.- 7. Computer-Aided Design and Analysis.- 7.1 Design flow for on-chip power distribution networks.- 7.2 Linear analysis of power distribution networks.- 7.3 Modeling power distribution networks.- 7.4 Characterizing the power current requirements of on-chip circuits.- 7.5 Numerical methods for analyzing power distribution networks.- 7.6 Summary.- 8. Inductive Properties of On-Chip Power Distribution Grids.- 8.1 Power transmission circuit.- 8.2 Simulation setup.- 8.3 Grid types.- 8.4 Inductance versus line width.- 8.5 Dependence of inductance on grid type.- 8.5.1 Non-interdigitated versus interdigitated grids.- 8.5.2 Paired versus interdigitated grids.- 8.6 Dependence of Inductance on grid dimensions.- 8.6.1 Dependence of inductance on grid width.- 8.6.2 Dependence of inductance on grid length.- 8.6.3 Sheet inductance of power grids.- 8.6.4 Efficient computation of grid inductance.- 8.7 Summary.- 9. Variation of Grid Inductance with Frequency.- 9.1 Analysis approach.- 9.2 Discussion of inductance variation.- 9.2.1 Circuit models.- 9.2.2 Analysis of inductance variation.- 9.3 Summary.- 10. Inductance/Area/Resistance Tradeoffs.- 10.1 Inductance vs. resistance tradeoff under a constant grid area constraint.- 10.2 Inductance vs. area tradeoff under a constant grid resistance constraint.- 10.3 Summary.- 11. Scaling Trends Of On-Chip Power Distribution Noise.- 11.1 Prior work.- 11.2 Interconnect characteristics.- 11.2.1 Global interconnect characteristics.- 11.2.2 Scaling of the grid inductance.- 11.2.3 Flip-chip packaging characteristics.- 11.2.4 Impact of on-chip capacitance.- 11.3 Model of power supply noise.- 11.4 Power supply noise scaling.- 11.4.1 Analysis of constant metal thickness scenario.- 11.4.2 Analysis of the scaled metal thickness scenario.- 11.4.3 ITRS scaling of power noise.- 11.5 Implications of noise scaling.- 11.6 Summary.- 12. Impedance Characteristics of Multi-Layer Grids.- 12.1 Electrical properties of multi-layer grids.- 12.1.1 Impedance characteristics of individual grid layers.- 12.1.2 Impedance characteristics of multi-layer grids.- 12.2 Case study of a two layer grid.- 12.2.1 Simulation setup.- 12.2.2 Inductive coupling between grid layers.- 12.2.3 Inductive characteristics of a two layer grid.- 12.2.4 Resistive characteristics of a two layer grid.- 12.2.5 Variation of impedance with frequency in a two layer grid.- 12.3 Design implications.- 12.4 Summary.- 13. Inductive Effects In On-Chip Power Distribution Networks.- 13.1 Scaling effects in chip-package resonance.- 13.2 Propagation of power distribution noise.- 13.3 Local inductive behavior.- 13.4 Summary.- 14. Conclusions.- References.- About the Authors.

Inductive properties of high-performance power distribution grids

The design of high integrity, area efficient power distribution grids has become of practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties permit the efficient estimation of the inductive characteristics of power distribution grids. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed performance distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground lines are considered.

Impedance characteristics of power distribution grids in nanoscale integrated circuits

The essential design characteristic of nanoscale integrated circuits is increased interconnect complexity. Conductors at different levels of the interconnect hierarchy have highly different physical and, consequently, electrical characteristics. These interconnect lines also exhibit inductive behavior due to enhanced switching speed of nanoscale devices, making interconnect design and analysis difficult. The design of robust and area efficient power distribution networks for high-speed integrated circuits has therefore become a challenging task. The impedance characteristics of multilayer power distribution grids and the relevant design implications are the subject of this paper. The power distribution network spans many layers of interconnect with disparate electrical properties. Unlike single-layer grids, the electrical characteristics of multilayer grids vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low-resistance upper layers to the low-inductance lower layers. The inductance of a multilayer grid therefore decreases with frequency, while the resistance increases with frequency. The lower layers of multilayer power grids provide a low-inductance current path, significantly reducing the grid impedance at high frequencies. Multilayer power distribution grids extend to the lower interconnect layers, exhibiting superior high-frequency impedance characteristics as compared to power distribution grids built exclusively within the upper, low-resistance metal layers. A significant share of metal resources to distribute the global power should therefore be allocated to the lower metal layers. An analytic model is also presented to determine the impedance characteristics of a multilayer grid from the inductive and resistive properties of the comprising individual grid layers.

Properties of on-chip inductive current loops

The variation of inductance with circuit length is investigated in this paper. The nonlinear variation of inductance with length is shown to be a result of inductive coupling among circuit segments. If the distance between the forward and return current paths of a current loop is much smaller than the loop length, the inductive coupling to the forward current is similar to the coupling to the return current, resulting in negligible coupling. The inductance of these circuits therefore varies approximately linearly with length. Similarly, the effective inductive coupling between two parallel current loops is reduced through cancellation and has a negligible effect on the net inductance of a circuit. As a general rule, the inductance of circuits where the distance between the forward and return current is much smaller than the characteristic dimensions of the circuit scales linearly with circuit dimensions. This linear behavior can be used to simplify the inductance extraction and circuit analysis process.

Inductive characteristics of power distribution grids in high speed integrated circuits

The inductive characteristics of several types of gridded power distribution networks are described in this paper. The inductance extraction program FastHenry is used to evaluate the inductive properties of grid structured interconnect. In power distribution grids with alternating power and ground lines, the inductance is shown to vary linearly with grid length and inversely linearly with the number of lines in the grid. The inductance is also relatively constant with frequency in these grid structures. These properties provide accurate and efficient estimates of the inductance of power grid structures with various dimensions.

Electrical characteristics of multi-layer power distribution grids

The design of robust and area efficient power distribution networks for high speed, high complexity integrated circuits has become a challenging task. The integrity of the high frequency signals depends upon the impedance characteristics of the on-chip power distribution networks. The electrical characteristics of these multi-layer power distribution grids and the relevant design implications are the subject of this paper. Each grid layer within a multilayer power distribution grid typically has significantly different electrical properties. Unlike single layer grids, the electrical characteristics of a multi-layer grid can vary significantly with frequency. As the frequency increases, a large share of the current flow is transfered from the low resistance upper layers to the low inductance lower layers. The inductance of a multi-layer grid therefore decreases with frequency, while the resistance increases with frequency. Therefore, as compared to power distribution grids built exclusively in the upper, low resistance metal layers, a multi-layer power distribution grid extending to the lower interconnect layers exhibits superior high frequency impedance characteristics. An analytic model is also presented to determine the impedance characteristics of a multi-layer grid from the inductive and resistive properties of the comprising individual grid layers.

Inductance/area/resistance tradeoffs in high performance power distribution grids

The design of high integrity, area efficient power distribution grids is of immediate practical importance as the portion of on-chip interconnect resources dedicated to power distribution networks in high performance integrated circuits has greatly increased. To optimize the process of allocating on-chip metal resources, inductance/area/resistance tradeoffs in high speed power distribution grids are explored. Two tradeoff scenarios in power grids with alternating power and ground rails are considered. In the first scenario, the area occupied by the grid lines is maintained constant and the grid inductance versus grid resistance tradeoff is evaluated as the width of the grid lines varies. In the second scenario, the metal area of the grid is maintained constant and the grid inductance versus grid area tradeoff is investigated. In both cases, the grid inductance increases almost linearly with line width, rising more then eightfold for a tenfold increase in line width. The grid resistance and grid area, however, decrease relatively slowly with line width. This decrease in grid resistance and area is limited to a factor of two under assumed interconnect characteristics.

On-Chip Power Delivery and Management

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks

Scaling trends of on-chip Power distribution noise

The design of power distribution networks in high-performance integrated circuits has become significantly more challenging with recent advances in process technologies. As on-chip currents exceed tens of amperes and circuit clock periods are reduced well below a nanosecond, the signal integrity of on-chip power supply has become a primary concern in the integrated circuit design. The scaling behavior of the inductive and resistance voltage drops across the on-chip power distribution networks is the subject of this paper. The existing work on power distribution noise scaling is reviewed and extended to include the scaling behavior of the inductance of the on-chip global power distribution networks in high-performance flip-chip packaged integrated circuits. As the dimensions of the on-chip devices are scaled by S, where S>1, the resistive voltage drop across the power grids remains constant and the inductive voltage drop increases by S, if the metal thickness is maintained constant. Consequently, the signal-to-noise ratio decreases by S in the case of resistive noise and by S/sup 2/ in the case of inductive noise. As compared to the constant metal thickness scenario, ideal interconnect scaling of the global power grid mitigates the unfavorable scaling of the inductive noise but exacerbates the scaling of resistive noise by a factor of S. On-chip inductive noise will, therefore, become of greater significance with technology scaling. Careful tradeoffs between the resistance and inductance of the power distribution networks will be necessary in nanometer technologies to achieve minimum power supply noise.