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Active Filter-Based Hybrid On-Chip DC–DC Converter for Point-of-Load Voltage Regulation

An active filter-based on-chip DC-DC voltage converter for application to distributed on-chip power supplies in multivoltage systems is described in this paper. No inductor or output capacitor is required in the proposed converter. The area of the voltage converter is therefore significantly less than that of a conventional low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for noise sensitive portions of an integrated circuit. The performance of the circuit has been verified with Cadence Spectre simulations and fabricated with a commercial 110 nm complimentary metal oxide semiconductor (CMOS) technology. The area of the voltage regulator is 0.015 mm2 and delivers up to 80 mA of output current. The transient response with no output capacitor ranges from 72 to 192 ns. The parameter sensitivity of the active filter is also described. The advantages and disadvantages of the active filter-based, conventional switching, linear, and switched capacitor voltage converters are compared. The proposed circuit is an alternative to classical LDO voltage regulators, providing a means for distributing multiple local power supplies across an integrated circuit while maintaining high current efficiency and fast response time within a small area.

Distributed On-Chip Power Delivery

The performance of an integrated circuit depends strongly upon the power delivery system. With the introduction of ultra-small on-chip voltage regulators, novel design methodologies are needed to simultaneously determine the location of the on-chip power supplies and decoupling capacitors. In this paper, a unified design methodology is proposed to determine the optimal location of the power supplies and decoupling capacitors in high performance integrated circuits. Optimization algorithms widely used for facility location problems are applied in the proposed methodology. The effect of the number and location of the power supplies and decoupling capacitors on the power noise and response time is discussed.

Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System

Dynamic power management techniques and related voltage converter architectures are proposed to design a secure and efficient on-chip power delivery system. A new power management technique, converter-gating, that adaptively turns on and off individual stages of an interleaved switched-capacitor voltage converter based on the workload information to improve the voltage conversion efficiency is proposed. Converter-gating technique is further utilized as a countermeasure against side channel power analysis attacks by pseudo-randomly controlling the converter activity. A new method is proposed to improve the response time of the converter during transient load changes by adaptively configuring the conversion ratio of a switched capacitor voltage converter. The proposed converter is designed and verified using IBM 130 nm technology kit. The proposed system achieves 5% higher power conversion efficiency compared to conventional converters, improves the response time to transient load changes from 1.4 μs to 104 ns and reduces the correlation between the input current and load current.

Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks

Side-channel attacks have become a significant threat to the integrated circuit security. Circuit level techniques are proposed in this paper as a countermeasure against side-channel attacks. A distributed on-chip power delivery system consisting of multi-level switched capacitor (SC) voltage converters is proposed where the individual interleaved stages are turned on and turned off either based on the workload information or pseudo-randomly to scramble the power consumption profile. In the case that the changes in the workload demand do not trigger the power delivery system to turn on or off individual stages, the active stages are reshuffled with so called converter-reshuffling to insert random spikes in the power consumption profile. An entropy based metric is developed to evaluate the security-performance of the proposed converter-reshuffling technique as compared to three other existing on-chip power delivery schemes. The increase in the power trace entropy with CoRe scheme is also demonstrated with simulation results to further verify the theoretical analysis.

Distributed power network co-design with on-chip power supplies and decoupling capacitors

With each technology generation, the power delivery network becomes larger and more complicated, making the system analysis process computationally complex. The rising number of on-chip power supplies and intentional decoupling capacitors inserted throughout an integrated circuit further complicates the analysis of the power distribution network. Interactions among the on-chip power supplies, decoupling capacitors, and load circuitry are investigated in this paper. The on-chip power supplies and decoupling capacitors within the power network are simultaneously co-designed and placed. The effect of physical distance on the power supply noise is investigated. This methodology changes conventional practices where the power distribution network is designed first, followed by the placement of the decoupling capacitors.

Power Noise in TSV-Based 3-D Integrated Circuits

A three-dimensional (3-D) test circuit examining power grid noise in a 3-D integrated stack has been designed, fabricated, and tested. Fabrication and vertical bonding were performed by MIT Lincoln Laboratory for a 150 nm, three metal layer SOI process. Three wafers are vertically bonded to form a 3-D stack. Noise analysis of three power delivery topologies is described. Calibration circuits for a source follower sense circuit compare the different power delivery topologies as well as the separate 3-D stacked circuits. The effect of the through silicon via (TSV) density on the noise profile of a 3-D power delivery network is experimentally described. A comparison of the peak noise for each topology with and without board level decoupling capacitors, and resonant behavior is provided, and suggestions for enhancing the design of a 3-D power delivery network are offered.

Fast algorithms for IR voltage drop analysis exploiting locality

Closed form expressions and related algorithms for fast power grid analysis are proposed in this paper. The IR voltage drop at an arbitrary point in a power distribution network is determined. Two algorithms are described for non-uniform voltage supplies and non-uniform current loads distributed throughout a power grid. The principle of spatial locality is exploited to accelerate the proposed power grid analysis method. Analysis of the non-uniform power grids utilizes the principle of spatial locality. Since no iterations are required for the proposed IR drop analysis, the proposed algorithms are over 70 times faster for smaller power grids composed of less than five million nodes and over 180 times faster for larger power grids composed of more than 25 million nodes as compared to existing methods. The proposed method exhibits less than 0.5% error.

An area efficient fully monolithic hybrid voltage regulator

A hybrid voltage regulator module for an on-chip DC-DC voltage converter is proposed in this paper. The circuit is appropriate for point-of-load voltage regulation due to an ultra area efficient architecture. The proposed voltage regulator is a hybrid combination of a switching DC-DC voltage converter and a low-dropout regulator exploiting active circuitry rather than bulky passive devices within the filter structure. The proposed circuit can supply over 100 mA current while generating 0.9 volts from a 1.2 input voltage, exhibiting a high current efficiency of greater than 99%. The on-chip area is 0.026 mm2 which is 500 times smaller than a monolithic buck converter and four times smaller than an LDO. The proposed regulator provides a means for distributing multiple local power supplies across an integrated circuit while providing high current efficiency.

Fast algorithms for power grid analysis based on effective resistance

The size of on-chip power distribution networks is increasing with each technology generation. Accurate and computationally efficient analysis of these power distribution networks has therefore become increasingly challenging. High performance power distribution networks are generally implemented as a uniform mesh structure. The uniformity of these power distribution networks can be exploited for fast, accurate nodal analysis. A closed form expression is presented here for determining the voltage at any arbitrary node in a power distribution network. The error of the proposed method as compared with SPICE is less than 0.2%. Since no iterations are required, the proposed method significantly outperforms previously proposed power grid analysis techniques in terms of computational speed while exhibiting low error.

Efficient algorithms for fast IR drop analysis exploiting locality

Closed-form expressions and related algorithms for fast power grid analysis are proposed in this paper. Four algorithms to determine the IR voltage drop at an arbitrary node are described when voltage supplies and current loads are non-uniformly distributed throughout a power grid. Two techniques are used to determine the effective impedance in a non-uniform and semi-uniform power grid. An effective resistance model is proposed for semi-uniform power grids. The principle of spatial locality is exploited to accelerate the proposed power grid analysis process. Since no iterations are required for the proposed IR drop analysis, the proposed algorithms are over 60 and two times faster for smaller power grids composed of less than five million nodes and over 175 and three times faster for larger power grids composed of more than 25million nodes as compared to, respectively, the random walk and second order iterative methods. The proposed method exhibits less than 0.3% error.