Inna P.-Vaisband

Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies

To provide a high quality power delivery system, the power needs to be regulated on-chip with ultra-small locally distributed power efficient converters. Historically, power efficient switching converters require large physical area, while compact linear power supplies exhibit high power conversion losses, which are not ideal for on-chip integration. To exploit the advantages of existing power supplies, a heterogeneous power delivery system is proposed. The power efficiency of the system is shown to be a strong function of the on-chip distribution of the power supplies. The optimal power distribution system with minimum power losses is determined by exhaustively comparing the power efficiency for all possible power supply topologies. A heterogeneous system with ten on-chip voltage domains and an optimal power distribution network has been evaluated, demonstrating up to 93% power efficiency. A power efficient clustering of the on-chip power supplies with linear computational complexity is also proposed. Heterogeneous power delivery systems with up to 100 on-chip voltage domains have been evaluated with power supplies distributed with linear computational complexity. A maximum 1.5% drop in power efficiency from the optimal solution has been observed, yielding a near optimal and high fidelity power supply distribution system.

A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 μm standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 μA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%.

On-Chip Power Delivery and Management

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks

Digitally Controlled Pulse Width Modulator for On-Chip Power Management

A digitally controlled current starved pulse width modulator (PWM) is described in this paper. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, permitting the duty cycle to vary between 25% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. A ring oscillator with two header circuits is proposed to control both duty cycle and frequency of the operation. Analytic closed-form expressions for the operation of a PWM are provided. The accuracy and performance of the proposed PWM is evaluated with 22-nm CMOS predictive technology models under PVT variations. An error of less than 3.1% and 4.4% in the duty cycle, respectively, with and without constant frequency control is reported for the PWM. A constant operation frequency with less than 1.25% period variation is demonstrated. The proposed PWM is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under PVT variations.

Stability of Distributed Power Delivery Systems With Multiple Parallel On-Chip LDO Regulators

High quality power delivery for high performance integrated circuits is a significant design challenge. To provide high quality power, the on-chip power needs to be regulated with ultrasmall locally distributed power efficient converters. While the quality of the power supply can be efficiently addressed with distributed on-chip power supplies, the stability of these parallel connected voltage regulators is a primary concern. A passivity-based stability criterion is proposed for maintaining a stable power delivery system composed of multiple regulators. To evaluate the proposed approach, a fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators has been fabricated in a 28 nm CMOS process. The experimental results of a distributed power delivery system composed of six on-chip LDO regulators satisfy this stability criterion, yielding a stable system response within -25°C to 125°C, 10% voltage variations, and 50% to 200% load sharing variations. The system is believed to be one of the first successful silicon demonstrations of stable parallel analog LDO regulators.

Energy efficient adaptive clustering of on-chip power delivery systems

Abstract Efficient on-chip power delivery is a significant design challenge in heterogeneous real time systems with multiple power domains. The power efficiency of the overall heterogeneous power delivery system has recently been shown to be a strong function of the clustering of the power supplies – the specific configuration in which the power converters and regulators are co-designed. A recursive clustering algorithm with polynomial computational complexity is proposed for a dynamically controllable power distribution system. The algorithm is evaluated on IBM power grid benchmark circuits, yielding up to a 21% increase in power efficiency, and orders of magnitude speedup in runtime.

Digitally controlled wide range pulse width modulator for on-chip power supplies

A digitally controlled current starved pulse width modulator is described in this paper. The current from the power grid to the ring oscillator is controlled by a header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, permitting the duty cycle to vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The accuracy and performance of the proposed digitally controlled pulse width modulator is evaluated with 22 nm CMOS predictive technology models under PVT variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations. Although the frequency of the switching signal is affected by changes in the duty cycle, the frequency variations are typically negligible.

Power efficient tree-based crosslinks for skew reduction

Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutions significantly increase the dissipated power, whereas existing link based methods only address skew caused by variations and do not consider power consumption. The power dissipated by the inserted crosslinks within a buffered clock tree is investigated in this paper, and is shown to be a strong function of the resistance and capacitance of the crosslink. A crosslink may be power efficient despite the presence of short-circuit currents caused by multiple drivers in a non-tree clock network. The power characteristics of crosslink size and placement are also discussed, showing that the crosslink is best placed as close as possible to the target leaves of the tree. Crosslink insertion as both an alternative and complement to buffer sizing for low power skew reduction is also considered.

Power Network-on-Chip for Scalable Power Delivery

Delivering high quality power to the on-chip circuitry with minimum energy loss is an essential component of integrated circuits. The quality of the power supply can be efficiently addressed with multiple power supplies and decoupling capacitors integrated on-chip close to the points-of-load. Distributed power delivery requires the co-design of hundreds of power converters with thousands of decoupling capacitors and billions of current loads within multiple power domains, significantly increasing the design complexity of existing power delivery systems. Efficient real-time management of the power budget in these complicated distributed power delivery systems is impractical with existing ad hoc approaches. The concept of a power network on-chip (PNoC) is introduced here as a systematic methodological solution for on-chip power delivery and management that provides enhanced power control and real-time management of resource sharing. A PNoC with four power domains is investigated based on the proposed architecture, and circuits for sensing, routing, and dynamic control of the on-chip power are described. The built-in modularity of the PNoC is exploited to apply dynamic voltage scaling, illustrating the scalability of the PNoC platform, while exhibiting power savings of up to 32%.

Inductance/Area/Resistance Tradeoffs

Tradeoffs among inductance, area, and resistance of power distribution grids are evaluated in this chapter. As discussed in Sect. 1.3, design objectives, such as low impedance (low inductance and resistance), small area, and low current densities (for improved reliability ), are typically in conflict. It is therefore important to make a balanced compromise among these design goals based upon application-specific constraints. A quantitative model of the inductance/area/resistance tradeoff in high performance power distribution networks is therefore necessary to achieve an efficient power distribution network. Another important goal is to provide quantitative guidelines to these tradeoffs and to bring intuition to the design of high performance power distribution networks.