Grzegorz Borowik

Fast Algorithm of Attribute Reduction Based on the Complementation of Boolean Function

In this chapter we propose a new method of solving the attribute reduction problem. Our method is different to the classical approach using the so-called discernibility function and its CNF into DNF transformation. We have proved that the problem is equivalent to very efficient unate complementation algorithm. That is why we propose new algorithm based on recursive execution of the procedure, which at every step of recursion selects the splitting variable and then calculates the cofactors with respect to the selected variables (Shannon expansion procedure). The recursion continues until at each leaf of the recursion tree the easily computable rules for complement process can be applied. The recursion process creates a binary tree so that the final result is obtained merging the results in the subtrees. The final matrix represents all the minimal reducts of a decision table or all the minimal dependence sets of input variables, respectively. According to the results of computer tests, better results can be achieved by application of our method in combination with the classical method.

5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs

The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.

Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's

Modern FPLD devices have a very complex structure. They combine PLA-like structures as well as FPGAs and even memory-based structures. However, the lack of an appropriate synthesis method does not allow the features of the modern FPLDs to be fully exploited. In this paper, an important problem of state assignment for an FSM as an extension of the previous research on ROM-based FSM implementation is presented. We pinpoint the sources of additional optimization of the functional decomposition and relate them to the state encoding conditions. The method is based on a reduction of a state assignment problem to a graph coloring problem. To this end, the so called multi-graph of incompatibility of memory T-words is applied. As a result, a new design technique for implementation of sequential circuits using embedded memory blocks of FPGAs has been developed. Preliminary experimental results are extremely encouraging.

Energy characteristic of a processor allocator and a network-on-chip

Energy characteristic of a processor allocator and a network-on-chip Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

Efficient logic controller design

Logic controller is a digital device used for automation of electromechanical processes, such as control of machinery on factory assembly line or lighting fixtures. This paper presents the method for designing a logic controller. We implement it using reprogrammable structure equipped with Embedded Memory Blocks, e.g. CPLD or FPGA. We find that specification of the controller with appropriate statechart diagram and further synthesis as equivalent Finite State Machine yields encouraging results: the number of programmable resources has been reduced approximately by 85%. Result of the research is illustrated with synthesis of practical controllers, where hardware resource consumption is presented. It shows the usefulness of the approach.1

Embedded Damage Localization Subsystem Based on Elastic Wave Propagation

This article presents an embedded signal processing subsystem constituting a part of a whole structural health monitoring system (SHM). Typical SHM system is responsible for elastic wave generation and sensing, signal acquisition, and signal processing. Signal processing subsystem was designed with the aim of localizing damage utilizing elastic wave propagation in the interrogated structure. The embedded signal processing subsystem is realized in a field programmable gate array chip, which also implements a damage localization algorithm designed for creating damage maps that can indicate elastic wave reflection sites within the investigated structure. Elastic waves are generated and received using a prototype electronic system developed specially for this purpose. Piezoelectric transducers are arranged in networks with different geometrical configurations (strip, cross, and square). Elastic waves are excited by a five-cycle tone burst signal with carrier frequency of 220 kHz. The investigated structure is a simple isotropic panel made out of aluminum alloy. First, dispersion curves are computed on the basis of registered elastic wave signals. These are subsequently used in the damage localization process. The damage localization process utilizes the base antisymmetric A0 mode. This article presents results of experimental verification of the developed damage localization algorithm as well as results of damage localization by the embedded subsystem.

Data Mining Approach for Decision and Classification Systems Using Logic Synthesis Algorithms

This chapter discusses analogies between decision system and logic circuit. For example, the problem of data redundancy in decision system is solved by minimizing the number of attributes and removing redundant decision rules which is analogous to the argument reduction method for logic circuits. Another issue associated with the field of data mining lies in the induction of decision rules which in result provide a basis for decision-making tasks. A similar algorithm in logic synthesis is called minimization of Boolean function. An issue of reduction of the capacity required to memorize a decision table is solved by disassembling this table to the subsystems in such a way that the original one can be recreated through hierarchical decision making. In logic synthesis it is called functional decomposition and is used for efficient technology mapping of logic circuits. Due to different interpretation and application these tasks seem totally different, however the analogies allow logic synthesis algorithms to be used in the field of data mining. Moreover, by applying specialized logic synthesis methods, these three issues, i.e. feature reduction, rule induction, and hierarchical decision making, can be successfully improved.

Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories

This paper presents a new cost-efficient realization scheme of pattern matching circuits in FPGA structures with embedded memory blocks (EMB). The general idea behind the proposed method is to implement combinational circuits using a net of finite state machines (FSM) instead. The application of functional decomposition method reduces the utilization of resources by implementing FSMs using both EMBs and LUT-based programmable logic blocks available in contemporary FPGAs. Experimental results for the proposed method are also shown. A comparison with another dedicated method yields extremely encouraging results: with a comparable number of EMBs, the number of logic cells has been reduced by 95%.

A First Attempt to Cloud-Based User Verification in Distributed System

In this paper, the idea of client verification in distributed systems is presented. The proposed solution presents a sample system where client verification through cloud resources using input signature is discussed. For different signatures the proposed method has been examined. Research results are presented and discussed to show potential advantages.

Benchmark Tests on Improved Merge for Big Data Processing

Computer scientists and engineers work with increasing amounts of information. These data are used for knowledge retrieval, data management decision support and so on. Sorting algorithms are important procedures that if efficiently composed and implemented can increase speed of data processing and decision correctness. Many various sorting algorithms and their modifications are applicable in large computer systems. However, as the computer architectures are more efficient with each release and the software is more complex with each version there is need to improve sorting methods applied for big data computation.