Tomasz Garbolino

A New LFSR with D and T Flip-Flops as an Effective Test Pattern Generator for VLSI Circuits

In the paper authors analyse properties of the various structures of linear registers (LFSRs) that are used as the test pattern generators in VLSI circuits. It is shown that the majority of them have one or more of the following drawbacks: • large area overhead that is caused by the large number of XOR gates, • reduced operational frequency due to presence of the long connection in the main feed-back loop and the high fan-out on the outputs of the flip-flops, • inflexible structure that cannot be easily redesigned and adjusted to the needs of the digital circuit efficient testing. In the paper we present a new type of LFSR that is free from all mentioned above disadvantages. We also develop the algebraic description of its operation and the methods of its designing. Finally we give numerous examples of its structures for different lengths of the register.

Genetic algorithm for test pattern generator design

The paper describes an approach for the generation of a deterministic test pattern generator logic, which is composed of D-type and T-type flip-flops. This approach employs a genetic algorithm that searches for an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches the proposed one reduces the gate count of a built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. The optimization includes the search for: the optimal combination of register cells type; the presence of inverters at inputs and outputs; the test patterns order in the generated test sequence; and the bit order of test patterns. Results of benchmark experiments and comparison with similar studies demonstrate the efficiency of the proposed evolutionary approach.

Test-per-Clock Detection, Localization and Identification of Interconnect Faults

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction. The above-mentioned operations are made at-speed. The testing process has been split into two steps. The first one is the detection step using a short test sequence of little diagnostic resolution. The second step is the localization step by means of a long, full diagnostic resolution sequence and it is made only in the case of the detection of faults in the first step. The final fault identification phase exploits information stored in the signatures. Because the signature is chosen to be 32 bit long aliasing is negligible. The proposed hardware concept is independent of the type of both the detection test sequence and the localization test sequence. The theory given in the paper is illustrated by the simulation results. Moreover the paper proposes to test testing hardware itself what makes the results reliable

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.

Interconnect Faults Identification and Localization Using Modified Ring LFSRs

In the paper a method of the fault detection, identification and localization by means of a ring LFSR (linear feedback shift register) is presented. The properties of a ring LFSR and the method to design a ring LFSR BIST is also given. Practical examinations of a ring LFSR application for localization faults in 8,16,24 and 32-bit buses are presented. Some important observations regarding the types of characteristic polynomials used in ring LFSRs are also included. Finally, the obtained results are summarised.

Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path

A new structure of the fast and low-area test pattern generator (TPG) composed of T-type flip-flops that can be easily integrated to the scan path is proposed in the paper. Nowadays, techniques of incorporating TPGs containing T-type flip-flops to the scan path either use asynchronous set and reset inputs of flip-flops or require adding a large amount of logic to transform TPG into the shift register. They all introduce large area overhead and degrade timing parameters of TPG. The area overhead of a new TPG structure is much less than in the case of to-day existing solutions. Moreover, it possess better timing parameters than conventionally designed TPGs. This last feature has been partially achieved due to the use of dedicated T-type flip-flop, whose design is presented in the paper. In addition, authors propose a testing method that is suitable for verifying correct functioning of both the scan-path and the new type TPGs incorporated in it.

Effective BIST for crosstalk faults in interconnects

The paper is devoted to a test-per-clock method of an length.

Optimal on-line built-in self-test structure for system-reliability improvement

This paper presents a bio-inspired technique for the generation of a deterministic test pattern generator. In contrast to conventional methods, the proposed evolutionary-based approach reduces the gate count of a built-in self-test structure, which is used for the automatic fault detection. The reduced-gate-count structure is needed to achieve the test structure with a smaller hardware area overhead, while still satisfying the reliability constraints. The presented optimization approach searches concurrently for the optimal combination of the register cells structure, the test patterns order in the generated test sequence, and the bit order of the test patterns. A comparison of the results with similar studies shows the efficiency of the proposed evolutionary approach, which is therefore very useful in the design of robust and fault-tolerant systems, while maintaining the minimum size of the hardware overhead.

Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor

The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The localization is done by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures

Test Pattern Generator Design Optimization Based on Genetic Algorithm

In this paper an approach for the generation of deterministic test pattern generator logic composed of D-type and T-type flip-flops is described. The approach employs a genetic algorithm to find an acceptable practical solution in a large space of possible implementations. In contrast to conventional approaches our genetic algorithm approach reduces the gate count of built-in self-test structure by concurrent optimization of multiple parameters that influence the final solution. Results of experiments with combinational benchmarks demonstrate the efficiency of the proposed evolutionary approach.