Witold A. Pleskacz

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits

This paper describes an algorithm for the extraction of the critical area for opens. The presented algorithm allows for the analysis of industrial size ICs with non-Manhattan geometry. Illustrative examples of the proposed algorithm, implemented by using design rule checker operations, are presented. It is shown that the extraction of the critical area for realistic size VLSI circuits designs can be done in an acceptable time.

CAD at the design-manufacturing interface

Owing to rapid changes of IC technologies, traditionaldesign rule checking is becoming inadequate to assure satisfactorylevels of IC manufacturability. This paper describes a newcomputer supported design analysis environment that improvesthe efficiency of manufacturability assessment of new products.This environment, called MAPEX 2, is described in the paperalong with some of its key procedures and algorithms. Illustrationsof MAPEX 2 applications and performance figures are provided as well.

Hierarchical defect-oriented fault simulation for digital circuits

A new fault model is developed for estimating the coverage of physical defects in digital circuits for given test sets. Based on this model, a new hierarchical defect oriented fault simulation method is proposed. At the higher level simulation we use the functional fault model, at the lower level we use the defect/fault relationships in the form of defect coverage table and the defect probabilities. A description and the experimental data are given about probabilistic analysis of a complex CMOS gate. Analysis of the quality of 100% stuck-at fault test sets for two benchmark circuits in covering physical defects like internal shorts, stuck-opens and stuck-ons. It has been shown that in the worst case a test with 100% stuck-at fault coverage may, have only 50% coverage for internal shorts in complex CMOS gates. It has been shown that classical test coverage calculation based on counting defects without taking into account the defect probabilities may lead to considerable overestimation of results.

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement

Abstract A new methodology of probabilistic analysis of CMOS physical defects in complex gates for the defect-based test is proposed. It is based on the developed approach for the identification and estimation of the probability of actual faulty functions resulting from shorts caused by spot defects in conductive layers of IC layout. The aim of this methodology is realistic representation of physical defects in fault models. The list of defects, identified faulty functions, defect coverage table, conditional defect probabilities, and effectiveness and optimal sequence of test patterns are the main output data of probabilistic-based faults characterisation. The description of such characterisation and experimental data obtained for industrial standard cell library in 0.8 μm CMOS technology are presented. Special software tool named FIESTA has been developed for the automation of the probabilistic-based fault characterisation. The main destination of this tool is the investigation of gates from Cadence standard cell library. The experimental data obtained during complex gates characterisation are used for the estimation of the physical defects coverage by hierarchical defect simulation. At the higher level simulation the developed functional fault model was used, at the lower level we used the defect/fault relationships in the form of the defect coverage table and the conditional defect probabilities. Analysis of the quality of 100% stuck-at fault (SAF) sets in relation to physical CMOS defects in complex gates was performed. The investigation of the correlation between the fault coverages for SAFs and defects of short type for two benchmark circuits was done as well.

Improvement of integrated circuit testing reliability by using the defect based approach

Abstract The systematic decrease in the minimum feature size in VLSI circuits makes spot defects an increasingly significant cause of ICs’ faults. A testing method optimized for detecting faults of this origin has been recently developed. This method, called defect based testing (DBT), requires a lot of computational effort at the stage of testing-procedure preparation, which makes it appear less attractive than the well-known stuck-at-fault oriented testing. This paper, however, shows that a stuck-at-fault-optimized test-vector set may prove highly inefficient in detecting spot-defect-induced faults. Experiments with the C17 ISCAS-85 testability benchmark show that the risk of a spot-defect damaged circuit passing the test is dangerously high if the test set was designed with stuck-at-faults in mind. It is also shown that although spot defects may in some cases transform a combinational circuit into a sequential one, in practice this phenomenon does not require any special treatment from the test designer. Eventually, a few methods are discussed that make the DBT less time consuming.

Enhanced LEON3 core for superscalar processing

Low power consumption and high-performance are two main directions in the development of modern microprocessor architectures. In general they are two excluding branches of System-on-Chip (SoC) evolution. The paper presents the methodology of enhancing LEON3 processor IP core with superscalar abilities for low-power or high-performance systems. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle with only one third increase in area occupation. The Enhanced LEON3 IP core was synthesized using UMC 90 nm CMOS technology.

A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations

A reistorless current reference source, e.g. for fast communication interfaces, has been described. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 55 ppm/°C temperature coefficient over range of −40 °C to 125 °C. Reference current susceptibility to process parameters variation is ±3 %. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than −127 dB and −103 dB, respectively.

Power Dissipation in Basic Global Clock Distribution Networks

In the paper power dissipation and maximal frequency of basic global clock distribution networks is analyzed. Basic topologies of trees and meshes were implemented and simulated in AMS CMOS 0.35 mum technology. Also, a circuit of basic ring oscillator was designed. The comparison of power dissipation and maximal working frequency between those structures was performed.

Hierarchical test generation for combinational circuits with real defects coverage

Abstract This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pattern generation (TPG) techniques taking into account physical defect localisation. A new parameter––probabilistic effectiveness of input patterns––has been used in the TPG technique with the goal of increasing real defect coverage. This parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits. This improvement has been implemented into the existing DefGen ATPG system for combinational circuits.

CAD tool for PLL Design

In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible. The created tool allows to analyze PLL parameters, like loop filter components values, VCO gain and charge pump current variations impact on loop stability and phase-noise. Algorithm for phase-noise calculation, based on transient PLL simulation, has also been implemented. Thanks to these features the created tool is a valuable aid for PLL designer on all design steps.