Diederik Verkest

Energy-aware compilation and hardware design for VLIW embedded systems

Tomorrows embedded devices need to run multimedia applications demanding high computational power with low energy consumption constraints. In this context, the register file is a key source of power consumption and its inappropriate design and management severely affects system power. In this paper, we present a new approach to reduce the energy of shared register files in forthcoming embedded VLIW processors running real-life applications up to 60% without performance penalty. This approach relies on limited hardware extensions and a compiler-based energy-aware register assignment algorithm to deactivate at run-time parts of the register file (i.e., sub-banks) in an independent way.

Compiler-driven leakage energy reduction in banked register files

Tomorrows embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption constraint. In this context, the register file is one of the key sources of power consumption and its inappropriate design and management can severely affect the performance of the system. In this paper, we present a new approach to reduce the energy of the shared register file in upcoming embedded VLIW architectures with several processing units. Energy savings up to a 60% can be obtained in the register file without any performance penalty. It is based on a set of hardware extensions and a compiler-based energy-aware register assignment algorithm that enable the de/activation of parts of the register file (i.e. sub-banks) in an independent way at run-time, which can be easily included in these embedded architectures.

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-of-line (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric <inline-formula> <tex-math notation=LaTeX>

A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs

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Exploration of system-level trade-offs for application mapping in multiprocessor system-on-chips

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System and method for hardware-software multitasking on a reconfigurable computing platform

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Enabling hardware-software multitasking on a reconfigurable computing platform for networked portable multimedia appliances

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Energy aware interconnect exploration of coarse grained reconfigurable processors

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Review Article: Linking EUV lithography line edge roughness and 16nm NAND memory performance

</tex-math></inline-formula> higher than the critical dimension control. For trench patterning using spacer-defined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%.

Large impact of task-level concurrency transformations on the MPEG4 IM1 player for weakly parallel processor platforms

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage (Vmin) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%-30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a 6σ yield target and an isoarea of SRAM bitcells, Vmin of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is 2.6× lower than LFET bitcells.