Angada B. Sachid

Field-Effect Transistors Built from All Two-Dimensional Material Components

We demonstrate field-effect transistors using heterogeneously stacked two-dimensional materials for all of the components, including the semiconductor, insulator, and metal layers. Specifically, MoS2 is used as the active channel material, hexagonal-BN as the top-gate dielectric, and graphene as the source/drain and the top-gate contacts. This transistor exhibits n-type behavior with an ON/OFF current ratio of >10(6), and an electron mobility of ∼33 cm(2)/V·s. Uniquely, the mobility does not degrade at high gate voltages, presenting an important advantage over conventional Si transistors where enhanced surface roughness scattering severely reduces carrier mobilities at high gate-fields. A WSe2-MoS2 diode with graphene contacts is also demonstrated. The diode exhibits excellent rectification behavior and a low reverse bias current, suggesting high quality interfaces between the stacked layers. In this work, all interfaces are based on van der Waals bonding, presenting a unique device architecture where crystalline, layered materials with atomically uniform thicknesses are stacked on demand, without the lattice parameter constraints. The results demonstrate the promise of using an all-layered material system for future electronic applications.

MoS2 transistors with 1-nanometer gate lengths

A flatter route to shorter channels High-performance silicon transistors can have gate lengths as short as 5 nm before source-drain tunneling and loss of electrostatic control lead to unacceptable leakage current when the device is off. Desai et al. explored the use of MoS2 as a channel material, given that its electronic properties as thin layers should limit such leakage. A transistor with a 1-nm physical gate was constructed with a MoS2 bilayer channel and a single-walled carbon nanotube gate electrode. Excellent switching characteristics and an on-off state current ratio of ∼106 were observed. Science, this issue p. 99 Molybdenum disulfide transistors with carbon nanotube gate electrodes have channel lengths below the silicon scaling limit. Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106. Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

High-Gain Inverters Based on WSe2 Complementary Field-Effect Transistors

In this work, the operation of n- and p-type field-effect transistors (FETs) on the same WSe2 flake is realized,and a complementary logic inverter is demonstrated. The p-FET is fabricated by contacting WSe2 with a high work function metal, Pt, which facilities hole injection at the source contact. The n-FET is realized by utilizing selective surface charge transfer doping with potassium to form degenerately doped n+ contacts for electron injection. An ON/OFF current ratio of >10(4) is achieved for both n- and p-FETs with similar ON current densities. A dc voltage gain of >12 is measured for the complementary WSe2 inverter. This work presents an important advance toward realization of complementary logic devices based on layered chalcogenide semiconductors for electronic applications.

Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve Ion. We propose the use of high-kappa spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si3N4 spacers, with kappa=20 spacers, we show that it is possible to achieve an 80% increase in Ion at iso-Ioff conditions and a 15% decrease in the inverter delay for a fan-out of four.

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in I_ON is not sufficient to improve the circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal-oxide-semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of I_ON, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same off-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts.

Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor

We report subthreshold swings as low as 8.5 mV/decade over as high as eight orders of magnitude of drain current in short-channel negative capacitance FinFETs (NC-FinFETs) with gate length Lg = 100 nm. NC-FinFETs are constructed by connecting a high-quality epitaxial bismuth ferrite (BiFeO3) ferroelectric capacitor to the gate terminal of both n-type and p-type FinFETs. We show that a self-consistent simulation scheme based on Berkeley SPICE Insulated-Gate-FET Model:Common Multi Gate model and Landau-Devonshire formalism could quantitatively match the experimental NC-FinFET transfer characteristics. This also allows a general procedure to extract the effective S-shaped ferroelectric charge-voltage characteristics that provides important insights into the device operation.

Sub-20 nm gate length FinFET design: Can high-κ spacers make a difference?

Sub-20 nm gate length FinFETs, are constrained by the very thin fin thickness (TFIN) necessary to maintain acceptable short-channel performance. For the 45 nm technology node and below, a novel device design methodology for undoped underlapped FinFETs with high-kappa spacers is presented to achieve higher circuit speed and SRAM cells with higher stability, lower leakage, faster access times and higher robustness to process variations compared to overlapped FinFETs. While comparing different FinFETs, we propose ON-current per fin as the parameter to be optimized instead of ON-current normalized to electrical width.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

We present the optimization of multiple-fin-height FinFET static random access memory (SRAM) to reduce cell leakage and improve the stability and density of SRAM. Using a taller fin FinFET for the pull-down device increases the read static noise margin of the SRAM and can potentially reduce the SRAM cell area. A reasonable amount of channel doping in all the transistors can be used to reduce the cell leakage current without appreciably degrading the stability of the SRAM cell. Increasing the channel doping of the access transistor simultaneously improves the read stability and decreases the cell leakage current of the SRAM cell.

A Novel and Robust Approach for Common Mode Feedback Using IDDG FinFET

In this paper, we propose a novel and robust approach for common mode feedback (CMFB) for a differential amplifier using independently driven double gate (IDDG) FinFET technology. The performance of a differential amplifier with and without the proposed CMFB scheme is compared using 2-D mixed mode device and circuit simulations. It is shown from extensive simulation results that it is possible to achieve a common mode rejection ratio of 90 dB with improved performance in terms of area, power, and bandwidth even in the presence of process variations. Stability analysis shows that the proposed CMFB scheme does not need any compensating network. The idea is validated using extensive mixed-mode circuit simulations on IDDG FinFET circuits in sub-45-nm node technologies.