Angela Arapoyanni

A CMOS charge pump for low voltage operation

This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2 V, 1.5 V, 1.2 V and 0.9 V an output voltage of 11.5 V, 8.4 V, 6.5 V and 4 V can be generated respectively, using five pumping stages.

A Built-In-Test Circuit for RF Differential Low Noise Amplifiers

This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid possible yield loss in case of a malfunctioning test circuitry. The technique has been evaluated on a typical CMOS RF DLNA and simulation results are presented.

A hierarchical architecture for concurrent soft error detection based on current sensing

Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the functional circuit under check.

Timing error tolerance in nanometer ICs

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be corrected by using a retry cycle.

A Built-In Voltage Measurement Technique for the Calibration of RF Mixers

A built-in technique to measure internal DC voltage levels used for the calibration of radio frequency (RF) mixers is presented in this paper. According to a common alternate test approach, RF mixer calibration is based on the prediction of the circuits performance characteristics that requires the acquisition of a set of DC voltage observables obtained from specific nodes of the mixer operating in homodyne mode. These observables, however, often correspond to internal nodes where direct access is not always possible. Furthermore, accurate calibration might require a relatively large set of voltage observables whose direct access would lead to a waste of resources and to increased cost. The proposed built-in technique provides digital readings for the DC levels at all nodes of interest through a single interface by exploiting the use of a voltage acquisition circuit implemented by a simple analog to digital converter, which consists of a ring-type voltage controlled oscillator and a counter. A reading correction method to minimize the uncertainty introduced by process variations and device mismatches in the acquisition circuit itself is also described. The efficiency of the proposed technique has been validated by its application to the calibration procedure of a typical differential RF mixer designed in a 0.18-μm CMOS technology. Simulation results have been obtained and assessed, both for the proposed built-in voltage measurement technique and for the direct voltage measurement approach, in favor of comparison.

A Design Technique for Energy Reduction in NORA CMOS Logic

In this work, a design technique to reduce the energy consumption in NO RAce (NORA) circuits is presented. The technique is based on a unidirectional switch topology combined with a new clocking scheme permitting both charge recycling between circuit nodes and elimination of the short circuit current. Calculations proved that energy savings higher than 20% can be achieved. Simulation results from NORA designs in a 0.18-mum CMOS technology are presented to demonstrate the effectiveness of the proposed technique to achieve both energy and energy-delay product reduction

Cost and power efficient timing error tolerance in flip-flop based microprocessor cores

Strengthening failure mechanisms accentuate timing errors as a real threat in nanometer technology microprocessor cores. In this work, we present a low-cost and low-power, multiple timing error detection and correction technique, which is based on a new flip-flop design. This flip-flop exploits a transition detector for error detection along with an asynchronous local error correction scheme to provide timing error tolerance. The proposed and the well known Razor techniques were applied separately in the design of two versions of a 32-bit MIPS microprocessor core using a 90nm CMOS technology. Comparisons based on the experimental results validate the efficiency of the new design approach.

A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

In this paper, a new Design for Testability (DFT) scheme is proposed, for the testing of LC-tank CMOS Voltage Controlled Oscillators (VCOs). The proposed test-circuit is capable of detecting hard (catastrophic) and soft (parametric) faults, injected in the VCO. The test result is provided by a digital Fail/Pass signal. Simulation results reveal the effectiveness of the proposed circuit. The overall silicon area requirement of the proposed DFT scheme is negligible.

A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs

We propose a new concurrent soft and timing error detection circuit that exploits the time redundancy approach to achieve tolerance with respect to transient and delay faults. The idea is based on current mode sense amplifier topologies to provide fast error detection times.