Yiorgos Tsiatouhas

A Built-In-Test Circuit for RF Differential Low Noise Amplifiers

This paper presents an efficient, low-cost, built-in test (BIT) circuit for radio frequency differential low noise amplifiers (DLNAs). The BIT circuit detects amplitude alterations at the outputs of the DLNA, due to parametric or catastrophic faults, and provides a single digital Pass/Fail indication signal. A triple modular redundancy approach has been adopted for the BIT circuit design to avoid possible yield loss in case of a malfunctioning test circuitry. The technique has been evaluated on a typical CMOS RF DLNA and simulation results are presented.

A hierarchical architecture for concurrent soft error detection based on current sensing

Robust circuit design techniques with respect to soft errors gain importance in the era of very deep submicron technologies. On-line testing will play an important role towards this direction. In this paper we propose a hierarchical architecture for concurrent soft error detection. This architecture is based on current sensing techniques and provides very low area overhead, small detection times and negligible performance penalty on the functional circuit under check.

Timing error tolerance in nanometer ICs

Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

In this paper a new circuit for concurrent soft and timing error detection in CMOS ICs is presented. The circuit is based on current mode sense amplifier topologies to provide fast error detection times. After an error has been detected it can be corrected by using a retry cycle.

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches

Multithreshold CMOS is very effective for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme can suffer from high sensitivity to process variations, which impedes manufacturability. We propose a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. The proposed design requires less design effort and offers greater power reduction and smaller area cost than the previous method. In addition, it can be combined with existing techniques to offer further static power reduction benefits. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.

A Robust and Reconfigurable Multi-mode Power Gating Architecture

Multi-threshold CMOS is a very effective technique for reducing standby leakage power during long periods of inactivity. Recently, a power-gating scheme was presented to support multiple power-off modes and reduce the leakage power during short periods of inactivity. However, this scheme suffers from high sensitivity to process variations, which impedes manufacturability and also limits its applicability to at most two intermediate power-off modes. We propose a new power-gating technique that is tolerant to process variations and scalable to more than two intermediate power-off modes. In addition, the proposed design requires minimum design effort and offers greater power reduction and smaller area cost than the previous method. Analysis and extensive simulation results demonstrate the effectiveness of the proposed design.

New High-Speed Multioutput Carry Look-Ahead Adders

In this brief, an efficient implementation of an 8-bit Manchester carry chain (MCC) adder in multioutput domino CMOS logic is proposed. The carries of this adder are computed in parallel by two independent 4-bit carry chains. Due to its limited carry chain length, the use of the proposed 8-bit adder module for the implementation of wider adders leads to significant operating speed improvement compared to the corresponding adders based on the standard 4-bit MCC adder module.

A Built-In Voltage Measurement Technique for the Calibration of RF Mixers

A built-in technique to measure internal DC voltage levels used for the calibration of radio frequency (RF) mixers is presented in this paper. According to a common alternate test approach, RF mixer calibration is based on the prediction of the circuits performance characteristics that requires the acquisition of a set of DC voltage observables obtained from specific nodes of the mixer operating in homodyne mode. These observables, however, often correspond to internal nodes where direct access is not always possible. Furthermore, accurate calibration might require a relatively large set of voltage observables whose direct access would lead to a waste of resources and to increased cost. The proposed built-in technique provides digital readings for the DC levels at all nodes of interest through a single interface by exploiting the use of a voltage acquisition circuit implemented by a simple analog to digital converter, which consists of a ring-type voltage controlled oscillator and a counter. A reading correction method to minimize the uncertainty introduced by process variations and device mismatches in the acquisition circuit itself is also described. The efficiency of the proposed technique has been validated by its application to the calibration procedure of a typical differential RF mixer designed in a 0.18-μm CMOS technology. Simulation results have been obtained and assessed, both for the proposed built-in voltage measurement technique and for the direct voltage measurement approach, in favor of comparison.

The use of pre-evaluation phase in dynamic CMOS logic

Dynamic logic families have been shown to offer performance advantages over traditional CMOS logic. Their operation is based on the use of a clock signal that provides two operation phases: the precharge phase and evaluation phase. The precharge phase is setting the circuit at a predefined initial state while the actual logic response is determined during the evaluation phase. In this paper we examine potential advantages when an additional phase, called pre-evaluation, is introduced. During this phase a restricted voltage swing occurs depending on the desired outcome. This voltage swing is amplified during the final evaluation in order to produce the final logic response. By restricting the required voltage swing at internal logic nodes (especially in case of those presenting high capacitance) we are able to achieve higher performance coupled with reduced power consumption.

Double node charge sharing SEU tolerant latch design

Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing mechanisms among these nodes, are a great concern in nanometer SRAMs, since pairs of cells are influenced. The concern is also extended to SEU related soft error tolerant latch designs, where multiple memory elements are exploited. In this work, we deal with double node charge sharing SEUs (DNCS-SEUs) that affect latch operation and we propose a new latch topology that it is capable to provide soft error tolerance under these new circumstances where single nodes or pairs of nodes are influenced by an SEU. Simulation results validate the efficiency of the new design.